mknox@EMX.UTEXAS.EDU (Margaret H. Knox) (11/26/88)
After sending Mike Morris a note about my Big-Z board (which turns out to be a REV-A) I saw Rusty's note about a Rev-B and -C. Rusty, if any of the notes you have fix a big glitch in one of the I/O lines, then I would sure be interested in any way I could get a copy of them (or a schematic, etc.). That glitch (pwrite, or some such) gives me trouble with most other non-Jade boards I've tried. Even hanging a few large capacitors around is only a "maybe" solution. Can I send you a SASE perhaps? tnx, mknox
rusty@cadnetix.COM (Rusty) (12/02/88)
In article <8811252334.AA04944@emx.utexas.edu> mknox@EMX.UTEXAS.EDU (Margaret H. Knox) writes: > ... > That glitch (pwrite, or some such) gives me trouble >with most other non-Jade boards I've tried.... >Can I send you a SASE perhaps? > > tnx, mknox well, first, here is a possible fix (from the manual): "Symptoms: The CPU card fails to operate with some dynamic memory cards at 4 MHz, and operates erratically with some disk controller cards at all operating clock rates." "Cause: <noise removed, summary is: they latched sWO*, sMEMR, and sINP using IC U40 (for rev C, anyway), a 7475/74LS75, clocked by pSYNCH. Quoting now: "The manual fails to mention that this takes the CPU board out of IEEE timing specifications"> "Cure: remove IC U40 and install a 16-pin dip header with jumpers installed between pins 2/16, 3/15, 6/10, 7/9. This removes the latch and does not introduce a pSYNCh delay for these signals" BTW, you GOTTA do this if you have an SD systems Expandoram II or the Jade DD disk controller (neat, huh? *THEIR* cards don't even work together!). There is also a fix for erratic reset (use a different cap value for C22), and for any problems with the serial port at 4 MHz (get a better 8251). ----- Rusty Carruth UUCP: {uunet,boulder}!cadnetix!rusty DOMAIN: rusty@cadnetix.com Cadnetix Corp. (303) 444-8075x681 \ 5775 Flatiron Pkwy. \ Boulder, Co 80301 Radio: N7IKQ 'home': P.O.B. 461 \ Lafayette, CO 80026