dg@lakart.UUCP (David Goodenough) (10/14/89)
I'm posting this to comp.os.cpm, since the question relates to a chip in my Televideo 803 CP/M machine. If anyone can recommend a better newsgroup to post to, please do so. Followups will go to comp.sources.wanted, or you can just E-mail them to me. The serial I/O chip in the Televideo 803 appears to be a hybrid cross between a CTC, PIO, and SIO, all in one package: the Mostek 3801. As delivered, the cpu has to poll the chip to receive incoming characters. I would like to write a serial driver that uses interrupts, but I haven't been able to find how to get the chip to generate an interrupt. I have run tests with all the vectors in the interrupt table filled in, but my suspicion is that I have to set a bit somewhere in a register to allow the chip to generate interrupts for received characters. Any ideas, hints, information, anything???? Thanks in advance, -- dg@lakart.UUCP - David Goodenough +---+ IHS | +-+-+ ....... !harvard!xait!lakart!dg +-+-+ | AKA: dg%lakart.uucp@xait.xerox.com +---+
RALPH@UHHEPG.BITNET (10/17/89)
Date: 16-OCT-1989 13:08:22.74
From: Ralph Becker-Szendy RALPH AT UHHEPG
To: GATEWAY::"INFO-CPM@WSMR-SIMTEL20.ARMY.MIL"
Subj: Re: Wanted - information on the Mostek 3801
Since that thing is a really beautifull chip (weird what turns one on), I'll
post a short description.
Mostek 3801 Z80STI (Serial Timer Interrupt), contains one full-duplex USART
with baud rate generator, 8 bit parallel IO with timers, and full interrupt
controller (Z80 compatible).
I will omit all the timers, since that gets really complicated, and you would
probably need the data sheet to make sense of it. Also, the break generation
and loopback mode of the USART will be skipped over:
It has four address lines, so 16 registers are directly addressable. 8 other
registers are indirectly addressable.
First the directly adressable ones (put address on A0-A3 and strobe):
0 IDR Indirect Data Register. To use an indirect register, write it's address
into the lowest three bits of the PVR (port ?), then access the
content of the requested indirect register through here.
1 GPIP General Purpose IO Interrupt. This is actually the parallel data
register. Read from it to determine the status of the 8 parallel input
lines, write to it to set their level. See the AER and DDR register for
setting the up I/O and defining their registers.
2 IPRB Interrupt Pending Register B. The bits in here are set if interrupt
channel 8-F have an interrupt request pending.
3 IPRA Interrupt Pending Register A. The bits in here are set if interrupt
channel 0-7 have an interrupt request pending.
4 ISRB Interrupt in Service Register B. The bits in here are set if interrupt
channel 8-F have an interrupt request currently in service. To end an
interrupt service, write a word with all ones, except a zero for the
interrupt channel you want to end the service on.
5 ISRA Interrupt in Service Register A. The bits in here are set if interrupt
channel 0-7 have an interrupt request currently in service. To end an
interrupt service, write a word with all ones, except a zero for the
interrupt channel you want to end the service on.
6 IMRB Interrupt Mask Register B. If any bit in here is cleared, the
corresponding interrupt channel 8-F is temporarily masked. Interrupts
can still become pending, bit will not go to the CPU.
7 IMRA Interrupt Mask Register A.If any bit in here is cleared, the
corresponding interrupt channel 0-7 is temporarily masked. Interrupts
can still become pending, bit will not go to the CPU.
8 PVR Pointer Vector Register. Contains the following bits (LSB first:)
IA0-IA2 Indirect Register Address
S Set this bit of you want to end every interrupt-service in
software, by clearing the appropriate bit in ISR. If this bit is
clear, end of interrupt service is signalled happens at RETI.
VR4 This bit is not modified by the chip. Write anything you like, and
read it back later.
V5-V7 The uppermost three bits of the interrupt vector.
9 TABCR Timers A and B Control Register.
A TBDR Timer B Data Register.
B TBDR Timer A Data Register.
C UCR USART Control Register. Contains the following bits (LSB first):
1 bit DMA enable. When using DMA, parallel pins 0 and 1 become outputs.
Pin 0 reflects the receive buffer full flag, pin 1 reflects the
transmit buffer empty flag.
1 bit Even/odd, if parity is used. Set for even, clear for odd.
1 bit Parity enable.
2 bit Start/Stop bits: =00 for synchroneous, =01 for ASync 1 stop bit,
=10 for ASync 1.5 stop bits, =11 for ASync 2 stop bits.
2 bit Word length: =00 for 8 bits, =01 for for 7 bits, -10 for 6 bits,
=11 for 5 bits.
1 bit Clock divider: Set for /16, clear for /1.
D RSR Receiver Status Register. Contains the following bits (LSB first):
- Receiver Enable. Clear this bit to disable the receiver.
- Sync strip. Set this bit, and sync characters will not be loaded into
the receive buffer. Also no buffer full or match signals will be
generated.
- Match / Character in Progress. In sync mode this is set whenever the
sync character is received. In async mode this is set whenever a
character is currently being shifted in.
- Break. Set in async mode if break is detected.
- Found/Search. Set this bit in sync mode if you want to hunt for the
sync word in the data stream.
- Frame error. Set in async mode if the stop bit was missing.
- Parity error. Set if the word received had the wrong parity.
- Overrun error. Set if a ward was received, but the receive buffer was
full.
- Buffer full. Set if there is a word waiting to be grabbed from the
receive buffer.
E TSR Transmitter Status Register. Contains the following bits (LSB first):
- Transmitter enable. Clear this bit to disable the transmitter output.
Also used for break generation.
- Low. Clear for normal operation. Set for special effects with break
and loopback.
- High. Set for normal operation. Clear for special effects with break
and loopback.
- Break. Set this to generate a break. This will create create a
transmitter error !
- End. This gets set at the end of the character being transmitted if
you disable the transmitter in the middle of a character.
- Auto turnaround. Set this bit to put the USART into loopback mode.
You have to manually enable and disable transmitter and receiver.
- Underrun error. Set if there was nothing to transmit. Usually you
can ignore this error.
- Buffer empty. Set when you can write a word into the transmit buffer.
F UDR USART Data Register.
And the indirectly addressable ones (see under IDR and PVR about how to access
them:
0 SCR Sync Character Register. Use in synchroneous mode of the USART.
1 TDDR Timer D Data Register.
2 TCDR Timer C Data Register.
3 AER Active Edge Register. This register determines on which edge of a
transition on the parallel input line a General Purpose interrupt will
be generated: Bit set for the 0-1 transition, bit clear for the 1-0
transition. You should configure the AER before enabling interrupts
using IERA and IERB.
4 IERB Interrupt Enable Register B. Set any bit in here to enable interrupts
from channel 8-F. Enable an interrupt by setting the corresping bit.
If an interrupt is disabled, it will never become pending.
5 IERA Interrupt Enable Register A. Set any bit in here to enable interrupts
from channel 0-7. Enable an interrupt by setting the corresping bit.
If an interrupt is disabled, it will never become pending.
6 DDR Data Direction Register. Determines whether the parallel port lines
are inputs or outputs: Bit set for output, bit clear for input.
7 TCDCR Timers C and D Control Register.
There are 16 interrupt channels:
1111 General Purpose 7 <--- highest priority
1110 General Purpose 6
1101 Timer A
1100 Receive Buffer Full
1011 Receive Error
1010 Transmit Buffer Empty
1001 Transmit Error
1000 Timer B
0111 General Purpose 5
0110 General Purpose 4
0101 Timer C
0100 Timer D
0011 General Purpose 3
0010 General Purpose 2
0001 General Purpose 1
0000 General Purpose 0 <--- lowest priority
The interrupt vector is made up as follows (MSB first):
- V7-V5 Uppermost three bits from the PVR
- Four bits interrupt channel number
- 0 to make it even.
If you want more information: SGS Thomson Microelectronics (formerly Mostek),
1310 Electronics Drive, Carrolton, TX 75006, (214)466-6000.
Disclaimer: I am in no way affiliated with SGS or Mostek, although I would like
to have some stock in them. I am just the happy owner of the data sheet for
this neat chip (which I haven't gotten around to actually using).
Ralph Becker-Szendy UHHEPB=24730::RALPH (HEPNet,SPAN)
University of Hawaii / High Energy Physics Group RALPH@UHHEPG.BITNET
Watanabe Hall #203, 2505 Correa Road, Honolulu, HI 96822 (808)948-7391