pevans@cynic.wimsey.bc.ca (Phillip Evans) (12/08/90)
Hello all - I am disassembling a boot prom and need to know some Z80DMA
and Z80DART stuff. The DMA gets sent 08hex as one of the first
instructions - then it's not used again by the prom. The DART gets
sent this sequence:
18 01 00 03 C1 04 44 05 68 00 (the last 00 might be superfluous)
to initialise it, and then the command port is only used by the
following bit of code.
FiddleP1:
XOR A ;zero A and reset flags
OUT (DARTAStat),A ;send it out
IN A,(DARTAStat)
AND 1 ;mask on bit 0
SCF ;set this in case it was set
RET Z ;ret if the bit was not set
OUT (DARTAStat),A ;SEE QUESTION TWO BELOW
IN A,(DARTAStat)
AND 'p' ;70H - mask bits 456
RET Z ;ret if none of the above set
IN A,(DATRADat)
LD A,'0' ;30H - load A without affecting flags
OUT (DARTAStat),A
OR A
RET
Question ONE:
What DOES the set of initialisation bytes do?
Question TWO:
What I need to know here are the meanings of the bits 0, 4, 5, and 6;
what happens when the status register is loaded with the returned byte
after it is masked with 0000 0001 binary; and what happnes when it is
loaded with 030hex.
No, I don't have a manual/set of data sheets, nor does either of the
libraries I tried.
Thanks in advance to anyone who can answer these questions for me...
tilmann@mcshh.hanse.de (Tilmann Reh) (12/09/90)
Hello. pevans@cynic.wimsey.bc.ca (Phillip Evans) writes: > The DMA gets sent 08hex as one of the first instructions - then it's > not used again by the prom. The DART gets sent this sequence: > 18 01 00 03 C1 04 44 05 68 00 (the last 00 might be superfluous) > Question ONE: What DOES the set of initialisation bytes do? a) The 08h for the DMA means: Port B is I/O and decrements. That seems to be not the whole initialization :-) b) 18 : channel reset 01 00 : all interrupts disable 03 C1 : rx 8 bit, no handshake, rx enable 04 44 : x16 clock mode, 1 stopbit, no parity 05 68 : dtr & rts inactive, tx 8 bit, tx enable 00 : reset internal register pointer > Question TWO: What I need to know here are the meanings of the > bits 0, 4, 5, and 6; The DART status register is as follows: bit 7 : break bit 6 : not used bit 5 : cts bit 4 : ri bit 3 : dcd bit 2 : tx buffer empty bit 1 : int. pending (ch. A only) bit 0 : rx char available > what happens when the status register is loaded with the returned byte > after it is masked with 0000 0001 binary; and what happnes when it is > loaded with 030hex. Be aware that you need only two addresses per channel, so the addresses of the status register and the command register are equal (see init part). So sending 00 to that address resets the internal register pointer (so that the next read-access will safely get the status register). The second output does exactly the same, as the value in A will always be 00. Outputting 30h to the command register means 'error reset'. Hope this may help you. > Thanks in advance to anyone who can answer these questions for me... no reason. Tilmann Reh tilmann@mcshh.uucp tilmann@mcshh.hanse.de