draco@chinet.UUCP (Kent D. Meyers) (11/30/86)
GIME2.TXT GIME Update - 21 Nov 86 (plus CoCo-3 misc.)
This is an addendum to GIME.TXT elsewhere in this Library.
Meant for all, but as FREE distribution only.
Please address info to Kevin Darling 73117,1375 for next update.
Let's keep the info flowing! The SIG purpose is to share knowledge.
Thanks to Greg Law and his friend Dennis W. for much register info.
Thanks to Others and Marsha (for my magnifier) on many of the pin-outs.
============================================================================
GIME Register Corrections:
$FF91 - Bit 5, Timer Input Select. Looks like 0=slower speed, instead. Haven't
had time to put a scope on it to check actual clocks, yet.
$FF92-3 - Interrupt Request Regs: You can also read these regs to see if there
is a LOW on an interrupt input pin. If you have both the IRQ and FIRQ for the
same device enabled, you read a Set bit on both regs if that input is low.
For example, if you set $FF02=0 and $FF92=2, then as long as a key is held
down, you will read back Bit 1 as Set.
The keyboard interrupt input is generated by simply AND'ing all the matrix
pins read back at $FF00. Therefore, you could select the key columns you wished
to get by setting the appropriate bits at $FF02 to zero. Pressing the key drops
the associated $FF00 line to zero, causing the AND output to go low to the
GIME. Setting $FF02 to all Ones would mean only the Joystick Fire buttons would
generate interrupts.
$FF94-95 - Storing a $00 at $FF94 seems to stop the timer. Also, apparently
each time it passes thru zero, the $FF92/93 bit is set without having to
re-enable that Int Request.
$FF98 - Bit 5 is the artifact color shift bit. Change it to flip Pmode 4
colors. A One is what is put there if you hold down the F1 key on reset. POKE
&HFF98,&H13 from Basic if your colors artifact the wrong way for you.
$FF9F - Horz Offset Reg. If you set Bit 7 and you're in Gfx mode, you can
scroll across a 128 byte picture. To use this, of course, you'd have to write
your own gfx routines. On my machine, tho, an offset of more than about 5
crashes.
$FFB0-BF - As I originally had, and we all know by now, FFB0-B7 are used for
the text mode char background colors, and FFB8-BF for char foreground colors,
in addition to their other gfx use.
============================================================================
CoCo-3 Internal Tidbits:
The 68B09E address lines finally have pullup resistors on them. Probably put
in for the 2MHz mode, they also help cure a little-known CoCo phantom: since
during disk access, the Halt line tri-states the address, data, and R/W lines,
some old CoCo's would float those lines right into writing junk in memory. Now
$FFFF would be presented to the system bus instead.
Since the GIME catches the old VDG mode info formerly written to the PIA at
$FF22, those four now-unconnected lines (PB4-7 on the 6821) might have some use
for us.
Also, Pin 10 of the RGB connector is tied to PB3 on the same PIA. Shades of
the Atari ST. Could possibly be used to detect type of monitor attached, if we
like.
Data read back from RAM must go thru a buffer, the GIME, and another buffer.
Amazing that it works at 2 MHz.
In case you didn't catch the hint from GIME.TXT on FF90 Bit 2, the option of
an internal SCS select opens up the possibility of a CoCo-4 with a built-in
disk controller.
============================================================================
GIME PINS:
. .
61 63 65 67 01 03 05 07 09 09 ------- 01 68 ------ 61
60 62 64 66 68 02 04 06 08 11 10 10 60
58 59 13 12 l l
56 57 15 14 l l
54 55 17 16 l l
52 53 Bottom 19 18 l Top l
50 51 21 20 l l
48 49 23 22 l l
46 47 25 24 l l
44 45 42 40 38 36 34 32 30 28 26 26 44
43 41 39 37 35 33 31 29 27 27 -------------------- 43
01 - GND 18 - D6 35 - +5 Volts 52 - A13
02 - XTAL 19 - D7 36 - Z3 53 - A14
03 - XTAL 20 - FIRQ* ->CPU 37 - Z4 54 - A15
04 - RAS* 21 - IRQ* -->CPU 38 - pullup 55 - VSYNC*
05 - CAS* 22 - CART* Int in 39 - Z5 56 - HSYNC*
06 - E 23 - KeyBd* Int in 40 - Z6 57 - D7 (RAM)
07 - Q 24 - RS232* Int in 41 - Z7 58 - D6
08 - R/W* 25 - A0 (fm CPU) 42 - Z8 59 - D5
09 - RESET* 26 - A1 43 - A4 (fm CPU) 60 - D4
10 - WEn* 0 27 - A2 44 - A5 61 - D3
11 - WEn* 1 28 - A3 45 - A6 62 - D2
12 - D0 (CPU) 29 - S2 46 - A7 63 - D1
13 - D1 30 - S1 47 - A8 64 - D0
14 - D2 31 - S0 48 - A9 65 - Comp Vid
15 - D3 32 - Z0 (RAM) 49 - A10 66 - Blue
16 - D4 33 - Z1 50 - A11 67 - Green
17 - D5 34 - Z2 51 - A12 68 - Red
Notes: WEnx = Write Enables for Banks 0 and 1 RAM
S2-0 = (address select code -> 74LS138) :
000 -0- ROM 010 -2- FF0X, FF2X 100 -4- int SCS 110 -6- norm SCS
001 -1- CTS 011 -3- FF1X, FF3X 101 -5- n/a 111 -7- ??ram??
============================================================================
CONNECTORS: (CN5,6 - top to bottom, CN2 - left to right)
CN6 - Gnd, +5, D1, D0, D2, D3, D6, D7, D5, D4, WEn1, Gnd
CN5 - Gnd, D2, D3, D1, WEn0, D0, CAS, D6, D5, D4, D7, Gnd
CN2 - Gnd, RAS, Z0, Z1 , Z2, Z3, Z4, Z5, Z6, Z7, Z8, Gnd
Note: Since a lot of this is by a QUICK observation, CHECK first if using!
Tho as far as the CN's go, even if I have messed up all but the CAS, RAS,
WEn's, and +5, you could connect the extra RAM Dx and Zx pins in parallel to
each bank in any order. The RAM's don't care.
CN6 and CN5 data lines go to separate 256K banks, of course.
============================================================================
General Info:
Data is written to the RAM by byte thru IC10 or IC11, selected by WEn 0 or 1.
(write enable 0 = even addresses, write enable 1 = odd addresses)
Two bank RAM data is read back to the GIME thru IC12 & IC13, byte at a time.
The CPU can then get it from the GIME by byte.
IC 10, 11, 12 = 74LS244 buffer. IC13 = 74LS374 latch clocked by CAS* rise.
RAM Read --> IC12 --> GIME enabled by CAS low. (read first)
RAM Read --> IC13 --> GIME enabled by CAS hi. (latched & read)
Test Points:
TP 2 = E TP 4 = RAS TP 6 = Comp Video TP 9 = Green
TP 3 = Q TP 5 = CAS TP 8 = Red TP10 = Blue