jhallen@wpi.wpi.edu (Joseph H Allen) (03/30/89)
In article <392@aucis.UUCP> you write: >I've always wanted to ask this.... > >On the front page of Electronic News, Dec. 7, 1987 issue, in an article >titled "Peripheral PC Kits Succumbing to Tightly Packed Chip Sets", there >is this paragraph: > > Although the standard architecture of the PC has provided the only > viable market for the consolidatied peripherals chip sets - a slight > silver lining to Motorla, which lost out to Intel's 8088 in th > original design-win because it could not deliver the 6809 MPU to IBM - > etc, etc. ^^^^ > >I have never heard of this before or after this specific article. Is it >true? If so, why would IBM have picked the 8 bit 6809 over the 16 bit >68000, which I belive was avaliable at roughly the same time? > >If true, just think of the possibilities, today we could have 33 Mhz CPU's >(32 bit) that were object code compatible with the 6809. > >Has anyone else heard this story? > > Jeff Easton > Zenith Data Systems I havn't heard this specific story but I suspect that the designers of the IBM were told to use an 8-bit processor, otherwise, why didn't they use the 8086 (which came out before the 8088 did)? Given that the designers were forced to pick an 8-bit processor, the 8088 is not at all a bad choice. If you totally ignore the segment stuff (set the segment registers equal), then the 8088 is not a bad 16-bit (not 3-bit like the 68000) processor (plus, an 8Mhz 8088 is faster than the corresponding 2Mhz 6809 because of the instruction look-ahead. Also, the 8088 has multiply, divide and more registers. Finally, the disgusting mnemonics can be fixed with a new assembler). So the real question is, why did the managers in charge of the IBM PC decide to make it an 8-bit machine? Also, I've heard another story: Did IBM own a significant amount of Intel (stock) when they designed the PC? - - - - 6809 is my favorite 8-bit processor. I've written huge assembly language programs for it (some were actually 48k) and I've picked up a few design hints over the years: If you're designing a 6809E system and you need to use DRAMS, you can use the dead cycle which appears in each instruction in the 6809 to safely refresh memory. Use a delayed AVMA signal to enable a counter output on the address bus (and to disable the processor's address and to step the counter). This way you can add transparent refresh with typically just 2 more chips and without having to double the speed of the DRAMs. Simple multitasking on the 6809: Use the DP register to point to an environment page which is used by each task and point the SP to the end of this page. This way small environment variables and scatch variables will appear at the beginning of this page and the stack will appear at the end of it. CLR instruction problems: The clear instruction does a read-modify-write. This can cause problems if you have memory separated by a set of latches. Fully protected demand paged virtual memory on the 6809: This can actually by done!! But it requires quite a bit of external logic: - put a prom in parallel with the processor such that when the processor does a fetch (I.E. LIC delayed) the prom decodes illegal instructions and resets (interrupts won't work) the processor. - put a 16 byte scratch ram onto the system so that when you get a task switch interrupt, you save the registers in this ram and not on the task's stack. You also have to use this ram to set-up what the registers are to have when you switch to a new task. There will have to be a bit of complicated logic (a counter to step through the ram and so on) to get this to work. - make a memory mapper with a 2k X 8 static ram. Have 4 of the address inputs select the current task and have the other 7 bits be the upper 7-bits of the address lines from the 6809. This way, you get 128 512-byte pages in 8 separate memory maps. Task switches occure very fast, all you have to do is save the 16 byte scratch ram mentioned above and set-up the stack with what the registers are to look like for the next task. Then do an interrupt return and change the 3-bit task number value. - hook 7 of the data bits from the 2kx8 ram to the address bus (in replacement of the original 7) and use the left over data bit for indicating page faults. You can also have a larger physical memory than the virtual memory by adding on a second 2kx8 ram in parallel to the first but with 8 more data (physical address) bits. - one last thing. You have to have a register somewhere which records the address of the fetch part of each instruction. This is so that you can re-execute the instruction when a page fault occures. This is a bit complicated since the software also has to figure out if the instruction did an increment or decrement and also if the page fault occured accross a page boundary, it has to figure this out.