[comp.sys.m6809] 68HC11 A/D Conversion Time Discrepancy

tsai@venus.ral.rpi.edu (Jodi Tsai) (06/08/90)

Dear comp.sys.m6809 readers,

  I have a discrepancy that I just can't seem to figure out. 
According to the Motorola M68HC11 Reference Manual, it takes
128 E cycles in order for the A/D result registers to contain 
valid conversion results.  The figure in the manual (Figure 12-4)
seems to indicate that it will take 128 E cycles before the 
CCF flag is set.  However, I have the following code running
in the 68HC11 and I always get "A/D conversion complete received
too soon".  In other words the conversion time for the A/D converter
is very short.  My E clock is the default of 2.0 MHz and I'm using
Multiple Channel Control.  Has anybody measured the conversion time of
the A/D converters of the 68HC11?  Is it close to 128 E cycles?  If so, 
how come my program doesn't wait that long?  

Please respond via e-mail and Thanks!!

;********************************************
;diagGetGripStats - get gripper stats
;	        Upon return,
;	A = position
;	B = crossfire
;	X = force1 and force2 in upper
;           and lower bytes of X respectively
;	Y = air valve loopback in upper byte
;*********************************************

diagGetGripStats ldaa	#ADCE4E7
		staa	ADCTL
		jsr	diagWaitCCF     ; wait for conversion complete flag
		ldy	ADR1		; get air value loopback in upper byte

		ldaa	#ADCE0E3
		staa	ADCTL
		jsr	diagWaitCCF	; wait for conversion complete
		ldaa	ADR1		; get position value
		ldx	ADR2		; get force values at ADR2 and ADR3
		ldab	ADR4		; get crossfire values

		rts

;************************************************
;diagWaitCCF - wait for conversion complete flag
;************************************************

diagWaitCCFErrMsg1 fcc	'A/D conversion never completed'
	        fcb	EOS

diagWaitCCFErrMsg2 fcc	'A/D conversion complete received too soon'
		fcb	EOS

diagWaitCCF	pshx			; save all registers
		psha
		pshb

		ldaa	#0
;
; Note, this loop in much less time than 128 E clocks
; so that the A register is incremented at least twice.
; This will verify that the A/D conversion time is reasonable
; 
diagWaitCCF1	inca
		cmpa	#$ff
		bne	diagWaitCCF2

		ldx	#diagWaitCCFErrMsg1
		jsr	diagError

diagWaitCCF2	ldab	#ADCCCF
		andb	ADCTL
		beq	diagWaitCCF1

		cmpa	1
		bhi	diagWaitCCF3

		ldx	#diagWaitCCFErrMsg2
		jsr	diagError

diagWaitCCF3	pulb			; restore all registers
		pula
		pulx
		rts
--
Jodi Tsai