VanGough@sandv.UUCP (Vincent Clarke) (04/12/91)
What is the proper way to use the interrupts for the GIME chip? I know the
addresses (bits 5 & 4 at ff90 to enable IRQ & FIRQ respectively, bits 5-0 at
ff92-3 to pick int. type, and prog. timer at ff94-5), but have had no luck
using them. Attempting to use the serial data input IRQ seemed to enable a
regular 60-hz int., instead of interrupting when data at the serial port
changed, as did the keyboard IRQ. What am I doing wrong? I disabled the
63.5 ms timer at ff00 and the 60 hz timer at ff02. Any help is much
appreciated.
V V
V V an Gough
vkdarling@hobbes.catt.ncsu.edu (Kevin Darling) (04/14/91)
VanGough@sandv.UUCP (Vincent Clarke) writes: >What is the proper way to use the interrupts for the GIME chip? I know the I think you asked me this in email not long ago (?), but my mail attempts bounced. One thing to know is that the serial interrupt is triggered on the wrong edge for most uses (altho some have figured ways around that (such as the OS-9 L-II "bitbanger" serial driver posted on Hayes BBS). Inverting it may help (or bypassing the coco's inverter chip which is inline). Here's the file I tried to send you: GIME Interrupt Operation: From test programs and 'scope probing, confirmed by Tandy later. Bit FF92/93 Enable/Status Bit Reference --- ----------------------------------- 7 n/a 6 n/a 5 Timer 4 Horz border . Enable bits = written to FF92/93 3 Vert border . Status bits = read from FF92/93 2 Serial data . CPU Interrupt = FIRQ/IRQ to cpu 1 Keyboard . FF92 = IRQ bit reg 0 Cartridge . FF93 = FIRQ bit reg SETTING ENABLE BIT - If source is currently valid (low), the status bit is immediately set and the cpu interrupt goes true. If source is not valid yet, then the next high->low edge will set the status bit and cpu interrupt line. AFTER CPU INTERRUPT - Reading a GIME status register resets the cpu interrupt, and ALL status bits (if any). This means that you must save the status register contents for later determination of which interrupts had come in. Turning off an enable bit (so that the source cannot trigger the GIME again) does not reset a cpu interrupt already pending. Only a status read will. If an external source line stays valid (low), such as the CART line might do with multiple MPI irq devices, then the GIME will not retrigger the cpu interrupt after the status read, unless you first disable, then reenable the appropriate bit (clear it and then set it again). best - kevin <kdarling@catt.ncsu.edu>