[comp.sys.hp] s700 questions answered

jeff@hpfcmgw.HP.COM (Jeff Taylor) (04/03/91)

>> Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.

> Are these external caches (sound too big to be on chip)?  How much
> (if any) delay does a cache access cost?  

IEEE Spectrum (April, 1991) has an article on page 58 entitled "How
ICs impact workstations" which describes "the design process employed
by a group of HP workstation designers in creating a prototype for a high
performance low-cost workstation ..."  The article states:

      The memory I/O controller was designed
    to work with 256K-by-4, 1M-by-4, or 4M-
    by-4-bit DRAMS. The timing and polarity of
    the control signals can be programmed at
    boot up time.  This allows different speeds
    of DRAMs and different loading (number of
    arrays) to be optimized. With 80-ns DRAMs,
    the memory system will fire first data back
    to the CPU 115 ns after the address has been
    received from the CPU. Subsequent data will
    be supplied at every 66-MHz clock edge.
      The memory controller is optimized to
    service cache misses to the CPU. The cache
    line size is 32 bytes...

For lots of additional information, see the article. Any typos are
mnie. I think that answers this question, but hey, I'm just a
software guy.

Hope this helps,
Jeff Taylor

cag@hpfcso.FC.HP.COM (Craig Gleason) (04/04/91)

>>> Cache: 128 kB instr/256 kB data (720, 730), 256 kB instr/256 kB data.
>
>> Are these external caches (sound too big to be on chip)?  How much
>> (if any) delay does a cache access cost?  
>
Yes, the caches are external.  They're implemented with industry standard
asynchronous SRAM's (15ns for the 50MHz systems, 12ns for the 66MHz ones).

Jeff's answer covers cache miss cases.  I might add that on both D-cache
and I-cache misses, execution proceeds when the missing data is supplied
("streaming") and continues to do so as the miss is processed.

On cache hits, the following applies:

Loads take only a single state on the cache address and data buses (we
issue a new load address each state).  The same goes for instruction 
fetches on the I-cache.  If the instruction following the load uses the
load data as an operand, there is a one state penalty (load-use).

Stores take three states on the D-cache.  This is a read-modify-write
operation combining a one state read with a two state write.  If the two
instructions following the store do not use the D-cache, the store will
appear to take only one state.  Otherwise, there will be one or two 
penalty states depending on when the next D-cache access is.  

eg.  store-load-add  :  two penalty states
     store-add-load  :  one penalty state
     store-add-add   :  no penalty

Craig Gleason
Hewlett-Packard