devil@techunix.BITNET (Gil Tene) (04/03/91)
Hello HPeople,
Question boils down to (explanation of motivation below) :
How do I do integer overflow detection on a 9000-7xx ?
(using machine code is OK)
Is it possible? Is it "cheap"? can it be done? can it be done without
using a whole signal call mechanism every time an overflow occurs?
Motivation:
I am thinking of porting a very high-CPU-consumption application
of mine that does Real Time simulation of some CPU (old) to the
new HP snake family. I have this spplication running on a 375.
In this application I do alot of machine code generation for the
simulated CPU instructions, sort of "on the fly" compilation of
one machine code to another. One of the key features that must
be properly simulated is the old CPU's overflow behaviour.
I seem to remember that the 800's RISC architecture doesn't have
overflow flags. I currently use the 68xxx's overflow flags for
overflow detection. Without this flag, or some other simple
integer overflow detection method (that is "cheap") I will have
to imbed generated code that will test for overflow conditions on
every simulated instruction (instead of a simple flag check).
AdvThanks,
-- Gil.
--
--------------------------------------------------------------------
-- Gil Tene "Some days it just doesn't pay --
-- devil@techunix.technion.ac.il to go to sleep in the morning." --
--------------------------------------------------------------------renglish@cello.hpl.hp.com (Bob English) (04/06/91)
devil@techunix.BITNET (Gil Tene) writes: > How do I do integer overflow detection on a 9000-7xx ? > (using machine code is OK) > Is it possible? Is it "cheap"? can it be done? can it be done without > using a whole signal call mechanism every time an overflow occurs? I don't know what high-level language support exists for this, but since you don't seem to care, I'll tell you about the machine level stuff. Instead of using condition codes, PA-RISC uses nullification to modify instruction streams. On many instructions, you can specify a condition which, if met, will cause the following instruction to be skipped or nullified. If, for example, you wanted to add the contents of register r1 to r2, and set the third bit of register r3 on overflow, you could use the following two instruction sequence: add,nuv r1,r2,r2 ; nullify if no unsigned overflow depi 1,3,1,r3 ; set bit three in r3 The instruction set has many such primitives (there are nullification codes for all varieties of overflow and non-overflow, for example), as well as instructions that combine branches with conditions. The best way to see the whole set is to get a copy of the PA-RISC Architecture and Instruction Set Reference Manual. I don't know how to order them, however; they just show up on my desk every once in a while :-). --bob-- renglish@hplabs.hp.com
huck@aspen.IAG.HP.COM (Jerry Huck) (04/06/91)
>In comp.sys.hp, devil@techunix.BITNET (Gil Tene) writes: > Hello HPeople, > Question boils down to (explanation of motivation below) : > How do I do integer overflow detection on a 9000-7xx ? > (using machine code is OK) > Is it possible? Is it "cheap"? can it be done? can it be done without > using a whole signal call mechanism every time an overflow occurs? The 9000-7xx and the 9000-8xx are both implementations of the PA-RISC architecture. The most effective way to do in-line overflow tests is to use instruction nullification. The special case of addition can be done in a single instruction. All compuations instructions (add, sub, add with carry,...) allow conditional nullification (cancelling) of the next instruction. For your purposes the sequence might be: ... sub,NSV r1,r2,r3 ;do an operation and skip the next ;if no signed overflow. depi 1,OVBIT,1,simulatedPSW ;set some bit (depi=deposit immediate) ... ;in some magic location on overflow. This turns those instructions that are simulating overflow setting instructions into a 2 instruction sequence. An alternative exists for 32 bit addition. If overflow is unlikely, you could use the instruction: ... addb,SV r1,r2,setoverflow ;r2<-r1+r2. Branch only on overflow. <delay slot> ;next instruction. Will be executed ;if branch is taken. You could also ;cancel this if necessary. rejoin: ... setoverflow: b rejoin depi 1,OVBIT,1,simulatedPSW ;set some bit (depi=deposit immediate) ... ;in some magic location. This style requires that 2 instruction out-of-line fix-up for each occurrence of an ADDB,SV occurrence. In your 68K hosted emulation, what is the overhead per simulated instruction that needs to record overflow? Do you put those flag tests (I assume a branch on condition) after each simulated potentially overflowing instruction or can you collect a bunch of operations before testing for overflow? Hope this helps, Jerry
dhandly@hpcupt3.cup.hp.com (Dennis Handly) (04/06/91)
>How do I do integer overflow detection on PA-RISC? (using machine code is OK) >Is it possible? Is it "cheap"? can it be done? can it be done without >using a whole signal call mechanism every time an overflow occurs? The add and subtract instructions have completers. You can nullify the next instruction if a condition is/isn't meet. Just make sure you don't use the ADDO or SUBO unless you want to trap. >Without this flag, or some other simple >integer overflow detection method (that is "cheap") I will have >to embed generated code that will test for overflow conditions on >every simulated instruction (instead of a simple flag check). Is the above two instructions for every add/subtract cheap enough? Of course if you don't have overflows often, you might just want to trap.