hugibaz@floenz2.UUCP (Ingo Kraupa) (09/08/89)
In article <9690@eerie.acsu.Buffalo.EDU> bowen@mira.cs.Buffalo.EDU (Devon Bowen) writes: >Distribution: world > >In article <2975@floenz2.UUCP>, hugibaz@floenz2.UUCP (Ingo Kraupa) writes: > >I recently built a similar thing, but mine is less than $15 in parts. Or >do you mean he's selling the full built and tested models at $30? I've got >PostScript version of the schematics for mine if anyone's interested. 15$ is about the prize of the parts, I think. I got one built for about 30$, so that's all I can say. > >> cartridge (for the C64). There _is_ software for the C128. >> Please ask me, if you are interested. > >I'm very interested in the software for the C128 if it's compatible with >my board. More info, please. I built mine specifically for a TCP package Here is the information: The pure cartridge contains nothing more than a ACIA 6551A, a crystal (1.8432 Mhz), and a MAX232. The software uses the non-maskable-interrupt for data receive, the location is at $de00. A real advantage: disk drive, printer and rs232 can be used at the same time. >Anyway, the 6551 is definitely the way to go. It takes all the overhead >off the 64 and really lets IO fly! Too bad it wasn't built in in the first >place... 8-( This is really true. Ingo
bowen@mira.cs.Buffalo.EDU (Devon Bowen) (09/11/89)
Distribution: world In article <2977@floenz2.UUCP>, hugibaz@floenz2.UUCP (Ingo Kraupa) writes: > Here is the information: > > The pure cartridge contains nothing more than a ACIA 6551A, a crystal > (1.8432 Mhz), and a MAX232. Hmm. Has this been tested on a variety of 64's and 128's? When I tried just these components, I had problems with 6551 timing. That's why I had to add the 74LS74. This is on a 128. Maybe the timing for the 64 allows it to work without the delay. > The software uses the non-maskable-interrupt for data receive, the location > is at $de00. Oh well, my task requires it to be on the IRQ. I guess I'll stick with mine... Devon
hugibaz@floenz2.UUCP (Ingo Kraupa) (09/12/89)
In article <10048@eerie.acsu.Buffalo.EDU> bowen@mira.cs.Buffalo.EDU (Devon Bowen) writes: >> The pure cartridge contains nothing more than a ACIA 6551A, a crystal >> (1.8432 Mhz), and a MAX232. > >Hmm. Has this been tested on a variety of 64's and 128's? When I tried just >these components, I had problems with 6551 timing. That's why I had to add >the 74LS74. This is on a 128. Maybe the timing for the 64 allows it to work >without the delay. It may be that you are using a 6551 chip (rather than a 6551a). When the timing problems occur in 2 Mhz-mode only, this is quite sure. > >> The software uses the non-maskable-interrupt for data receive, the location >> is at $de00. > >Oh well, my task requires it to be on the IRQ. I guess I'll stick with mine... IRQ is fine unless there will come an SEI... On my cartridge are dip-switches to solve this problem. Ingo ___ _, _______ _______ / \ __(_)__ |One way\ .^... |End of | Ulbe says: "I go to the but- STOP! (Q.o) |traffic > |(O,O) | road | cher and give him a butcher" \___/ ,-<`-')-' |_______/ `<`=')--^ |_______| .... ..- --. .. -... .- --.. | \~/ | \./ | Ingo Kraupa /\ Quittenweg 42 _|_ ./|_ _|_ _|\, _|_ 8510 Fuerth \/ +49 911764074
Geoffrey.Welsh@p0.f171.n221.z1.fidonet.org (Geoffrey Welsh) (09/13/89)
> From: hugibaz@floenz2.UUCP (Ingo Kraupa) > Message-ID: <2979@floenz2.UUCP> > It may be that you are using a 6551 chip (rather than a 6551a). > When the timing problems occur in 2 Mhz-mode only, this is quite sure. I/O chips on the C128 run at 1 MHz, regardless of CPU speed. (This made doing cycle counting for DesTerm's 9600 bps code a wee bit difficult; I had to consider which cycles had to be stetched to 1 MHz to access I/O chips...) -- Geoffrey Welsh - via FidoNet node 1:221/171 UUCP: {{uunet!}watmath!xenitec!}zswamp!171.0!Geoffrey.Welsh ARPA: Geoffrey.Welsh@p0.f171.n221.z1.fidonet.org
daveh@cbmvax.UUCP (Dave Haynie) (09/15/89)
in article <2979@floenz2.UUCP>, hugibaz@floenz2.UUCP (Ingo Kraupa) says: > In article <10048@eerie.acsu.Buffalo.EDU> bowen@mira.cs.Buffalo.EDU (Devon Bowen) writes: >>> The pure cartridge contains nothing more than a ACIA 6551A, a crystal >>> (1.8432 Mhz), and a MAX232. >>Hmm. Has this been tested on a variety of 64's and 128's? When I tried just >>these components, I had problems with 6551 timing. That's why I had to add >>the 74LS74. This is on a 128. Maybe the timing for the 64 allows it to work >>without the delay. > It may be that you are using a 6551 chip (rather than a 6551a). > When the timing problems occur in 2 Mhz-mode only, this is quite sure. Actually, the timings from the Expansion port are roughly the same for 2MHz and 1MHz on a C128 (I think 2MHz is even slightly better in some respects, but I don't recall the details). The reason, of course, is that in 1MHz mode, the VIC is on that bus for 1/2 the cycle. Now, as to the 6551. There's a specified address setup to PHI and CS time that must be respected. If you simply run the PHI clock to the 6551 PHI2 input and one of the I/O lines to the CS input, you aren't doing it correctly. I think the timing is worse for this on the C64 than the C128. In general, there's more access time on the C128 expansion port than on the C64 expansion port. -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
daveh@cbmvax.UUCP (Dave Haynie) (09/15/89)
in article <840.250E60EC@zswamp.fidonet.org>, Geoffrey.Welsh@p0.f171.n221.z1.fidonet.org (Geoffrey Welsh) says: > > It may be that you are using a 6551 chip (rather than a 6551a). > > When the timing problems occur in 2 Mhz-mode only, this is quite sure. > I/O chips on the C128 run at 1 MHz, regardless of CPU speed. Well, yes and no. You always have basically the same timing available on the C128 user port, regardless of the clock speed. The only clock available on that port is the 1MHz PHI0 clock. Internally, the CPU is running off a different clock, which is the one that changes between 1MHz and 2MHz. If you're running at 2MHz and talking to an I/O device, the 1MHz and 2MHz clocks will always be synchronized. Half the time the 2MHz clock gets stretched to line up with the 1MHz clock, the other half of the time it falls such that it's naturally lined up. Now I know what you're thinking, "Sure sounds to me like you end up talking to the Expansion port at 2MHz, at least in that second case". If that's what you're thinking, you win the cupie doll -- that's exactly what's happening, at least in 6502 terms. A 1MHz part expects to get the while CPU cycle, both low and high portions of the clock. Addresses generally come valid before you're 1/2 way through the low 1/2, which means you can assure those long address setup to PHI2 times for parts like the 6551 no-problem. Only that's a generic 6502, not the C128 or C64. On these machines, the CPU is off the bus during the low portion of the PHI clock; VIC is on instead. So you only get to use the high portion of the PHI clock. Guess what. When you're in 2MHz mode, exactly the same thing happens -- a 2MHz cycle completely fits within the high portion of the PHI clock. So the Expansion Port was essentially running at 2MHz all along, it just wasn't all that obvious. > Geoffrey Welsh - via FidoNet node 1:221/171 -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
hugibaz@floenz2.UUCP (Ingo Kraupa) (09/18/89)
In article <7911@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes: > >Actually, the timings from the Expansion port are roughly the same for >2MHz and 1MHz on a C128 (I think 2MHz is even slightly better in some >respects, but I don't recall the details). The reason, of course, is >that in 1MHz mode, the VIC is on that bus for 1/2 the cycle. > >Now, as to the 6551. There's a specified address setup to PHI and CS >time that must be respected. If you simply run the PHI clock to the 6551 >PHI2 input and one of the I/O lines to the CS input, you aren't doing it >correctly. I think the timing is worse for this on the C64 than the C128. ^^^^^^^^^^ What do I have to do to make it correctly? I'm not a hardware specialist and in need of help. There _are_ some problems with the current thing; very mysterious for me. For example, when I receive something in full speed, at any baud rate, errors will occur. This is the same at 300 as at 19200 bps. Using a terminal with a piece of delay for upload, there is no error. Well, there aren't very much errors, but there shouldn't be any. Hope you can help me, Ingo