bruceh@pnet06.cts.com (Bruce Henderson) (07/19/88)
It appears as if the 88000 mac post is causing a stir. Good, I think that Apple needs to make one. Anyhow as the Mac 88000 torch bearer, here's some opinions on recent posts. <dre%ember@Sun.COM (David Emberson)> >At this point, I would think that the high cost of the 88000 chipset would >be prohibitive for a low cost machine. Also, the Harvard architecture, >while allowing reduced CPI in the absence of an on-chip I cache, requires >more external components. If Apple were to do a RISC machine now, the >only processors that would meet the cost constraint would probably be the >LSI Logic SPARC or Mips cpus which will be available as macros, the Fujitsu >SPARC, or possibly the 29K. My guess is that they will stay with 68030/40/50 >for some time. > Dave Emberson (dre@sun.com) >p.s. The only thing that Sun controls about SPARC is the trademark. Many >licensees are already designing SPARCs of all flavors on their own. Obviously >we have some clout, because at the moment we are the biggest consumer of >SPARC chips. But we don't (and couldn't possibly) "control" the SPARC vendors. the reasons SPARC is NOT the way to go. 1. Speed: The SPARC at 16Mhz is a capable processor. But the fact that is has only one bus for both instruction and data vice the 88000's Harvard bus means that the SPARC will have to jam twice as much data through the same channel. From my point of view that sounds like a bottleneck. The MC 88000 benchmarks at 34,000 Drystones compared to the SPARC's 19,000, yes the SPARC in question was only running at 16Mhz vice the 88000's 20Mhz, but if you scale the ratio to 20Mhz on the SPARC, it still only comes out to 23,750 Drystones. And if that weren't enough, when Motorola releases the 25Mhz 88K in November, that will be 42,000 drystones. Sun rates the SPARC at 10 MIPS.... but at least one indepenent tester has found it's closer to 6-8 MIPS. The 88000 is 13 to 17 mips in single processor format. with as much as 50 MIPS in a 4 processor cluster. 2. Programming The SPARC as no bit field instructions. In assembly language life is a bitch if you ever wanted to test bit 4 to see if it is high... The SPARC uses a Status Control Regester[SCR]. This is A-J OK if you haved a CISC design, but if you were going to try and execute more than 1 instruction per clock cycle, you are going to find that there may be more than 1 part of the CPU tring to manipulate the Status Regester at once. That could cause some intersting Branch conditions.... On average the SPARC takes more instructions to do the same task. This is probably what causes the diffrence in predicted and delivered MIPS rating. So there you have a few very obvious differences. I also think that While Sun is a fine company, they will never have the base of support in the area of day to day tasks that engineers spend 60% to 85% of thier day doing that Apple does. And the migration to an 88000 Mac could be made easily, providing Apple works towards a machine that is 80% to 100% source code compatible. Bruce Henderson asm... UUCP: hodge.cts.com!pnet06!bruceh ARPA: hodge!pnet06!bruceh@crash nosc.mil INET: bruceh@pnet06.cts.com