[comp.sys.mac] MACPLUS hardware question

betz@runx.ips.oz (Andrew Betzis) (12/28/88)

??	Has anyone had experience in interfacing to the MacPlus via the 68K? 
The problem I have is trying to have data ready by the time DTACK/ is
sampled in a normal MacPLus BUS cycle. Is there any way (without modifying
the CPU board) to delay DTACK/ so that a data transfer would take two normal
BUS cycles? Another way would be through VPA, VMA but is would take at least
three normal BUS cycles.

thanks & :-)
Andrew Betzis.

ACSnet: betz@runx.ips.oz		JANET:	runx.ips.oz!betz@ukc
ARPA:   betz%runx.ips.oz@seismo.css.gov	CSNET:	betz@runx.ips.oz
UUCP:  {enea,hplabs,mcvax,prlb2,seismo,ubc-vision,ukc}!munnari!runx.ips.oz!betz