mym@tybalt.caltech.edu (Mike Meckler) (09/21/89)
I was told yesterday, much to my surprise, that one cannot mix speeds of memory chips in one machine. I've known that I can't use slow memory in my Mac II, but this person told me that if I took my 2 meg Mac II, with its 120 ns memory, and replaced one of the banks with 80 ns chips from, say, Chip Merchant, then I would start to get random memory errors. "Usually when you're doing a large compilation," he threatened. Is this true? "Some people say my philosophy is kindergarten meckler@csvax.caltech.edu nihilism, but I say they don't truly exist." ...!ames!elroy!csvax!meckler
hodas@eniac.seas.upenn.edu (Josh Hodas) (09/21/89)
In article <11979@cit-vax.Caltech.Edu> mym@tybalt.caltech.edu.UUCP (Mike Meckler) writes: >I was told yesterday, much to my surprise, that one cannot mix speeds of >memory chips in one machine. I've known that I can't use slow memory in my >Mac II, but this person told me that if I took my 2 meg Mac II, with its >120 ns memory, and replaced one of the banks with 80 ns chips from, say, >Chip Merchant, then I would start to get random memory errors. "Usually >when you're doing a large compilation," he threatened. > >Is this true? No. At least not as far as I can tell, and I am running exactly that combination. I do believe that there is a restriction on mixing speeds in one grouping (ie one bank of 4 on a II, one row of 2 on a plus/se), but even this I have never heard difinitively confirmed. Josh ------------------------- Josh Hodas (hodas@eniac.seas.upenn.edu) 4223 Pine Street Philadelphia, PA 19104 (215) 222-7112 (home) (215) 898-5423 (school office)
dorourke@polyslo.CalPoly.EDU (David M. O'Rourke) (09/21/89)
mym@tybalt.caltech.edu.UUCP (Mike Meckler) writes: > [ some questions about mixing memory speeds ] It's my understanding that you are allowed to mix memory speeds on a bank by bank basis. On Mac II class machines that means you can mix in groups of 4, and on a 68000 class machine you can mix in groups of 2. But if you do mix banks you have to make sure that the chips are <= 120ns in a Mac II class machine. Don't know the minimum speed for a plus. Also somewhere in the back of my mind I seem to remember that even if you put faster chips in a Mac II {IIci excluded here I believe} that it doesn't matter since the system doesn't really take advantage of the additional speed of the chips. Any hardware types care to help me out here.... Hope this helps. -- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\|///////////////////////////////////////// David M. O'Rourke____________________|_____________dorourke@polyslo.calpoly.edu | God doesn't know, he would have never designed it like that in the first | |_ place. ____________________________________________________________________|
roy@phri.UUCP (Roy Smith) (09/22/89)
In <11979@cit-vax.Caltech.Edu> mym@tybalt.caltech.edu.UUCP (Mike Meckler):
-> [...] this person told me that if I took my 2 meg Mac II, with its
-> 120 ns memory, and replaced one of the banks with 80 ns chips [...] I
-> would start to get random memory errors
Bullshit.
--
Roy Smith, Public Health Research Institute
455 First Avenue, New York, NY 10016
{att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu
"The connector is the network"jh0576@leah.Albany.Edu (Joe Houghtaling) (09/22/89)
In article <4002@phri.UUCP>, roy@phri.UUCP (Roy Smith) writes: [in response to an inquiry on mixing speeds of memory chips] > Bullshit. Please, if you can't make a constructive addition to the net, at least don't be insulting. ------------------------------------------------------------------------ Joe Houghtaling jh0576@leah.albany.edu
kaufman@Neon.Stanford.EDU (Marc T. Kaufman) (09/22/89)
In article <2040@leah.Albany.Edu> jh0576@leah.Albany.Edu (Joe Houghtaling) writes: >In article <4002@phri.UUCP>, roy@phri.UUCP (Roy Smith) writes: > [in response to an inquiry on mixing speeds of memory chips] -> Bullshit. >Please, if you can't make a constructive addition to the net, at least >don't be insulting. I rise to Roy Smith's defense. That IS a constructive comment -- to the effect that: the folklore that says you can't mix memory speeds (subject to the requirement that each memory module is itself adequately fast) -- is Bullshit. Now I know that one doesn't have to be an EE to own and operate a computer. But we don't have to be afraid of them, either. There is a lot of tolerance in the design of a computer just so spot shortages of a particular chip, or a low-tolerance part, won't make the machine unbuildable. That's why so many (IBM) clone makers can push nominal 16 MHz machines to 20MHz -- as long as you don't get them too hot. If you want to cause trouble, why don't we start the rumor that using faster memory chips will invalidate the FCC clearance because the faster rise times radiate more... Marc Kaufman (kaufman@Neon.stanford.edu)
jh34607@suntc.UUCP (john howell) (09/23/89)
In article <11979@cit-vax.Caltech.Edu>, mym@tybalt.caltech.edu (Mike Meckler) writes: > I was told yesterday, much to my surprise, that one cannot mix speeds of > memory chips in one machine. I've known that I can't use slow memory in my > Mac II, but this person told me that if I took my 2 meg Mac II, with its > 120 ns memory, and replaced one of the banks with 80 ns chips from, say, > Chip Merchant, then I would start to get random memory errors. "Usually > when you're doing a large compilation," he threatened. > > Is this true? > No! No matter what the speed of the memory is, it will run at 120 ns. No faster. The faster memory chips just have been tested to run faster and are therefore worth more money. You do not need to be concerned about where the SIMMS go as long as they are grouped in groups of 4 by SIZE, not speed. Just make sure they are all at least 120 ns chips or faster, unless of course you have a new ][ci, then they all need to be 80ns or faster. John
allbery@NCoast.ORG (Brandon S. Allbery) (09/23/89)
As quoted from <2040@leah.Albany.Edu> by jh0576@leah.Albany.Edu (Joe Houghtaling): +--------------- | In article <4002@phri.UUCP>, roy@phri.UUCP (Roy Smith) writes: | [in response to an inquiry on mixing speeds of memory chips] | > Bullshit. | | Please, if you can't make a constructive addition to the net, at least | don't be insulting. +--------------- He was insulting only to the person who claimed to the original poster that the memory speeds *had* to match. (His dealer, if I remember correctly.) Said dealer may be trying to make him pay more than he has to, or he may simply not know any better, but either way his claim is bogus. (semi-techie explanation; my field is software, but I've dealt with memory) There is, by and large, only *one* case where the memory speeds would have to match: if the memory storage system accesses more than one memory chip at the same time, all of those chips must be the same speed or the memory access hardware will get a severe case of heartburn. Of course, the Mac *does* access more than one chip at the same time; but that's why the constraint is on *banks* of SIMMs. The Mac memory hardware requires speeds to be the same over a bank of memory because a memory access is actually 16 bits (68000) or 32 bits (68020/030); thus, a SIMM bank is two SIMMs on an SE (2 * 8 RAM chips per SIMM) and four (4 * 8) on the II and its descendants. ++Brandon -- Brandon S. Allbery, moderator of comp.sources.misc allbery@NCoast.ORG uunet!hal.cwru.edu!ncoast!allbery ncoast!allbery@hal.cwru.edu bsa@telotech.uucp, 161-7070 BALLBERY (MCI), ALLBERY (Delphi), B.ALLBERY (GEnie) Is that enough addresses for you? no? then: allbery@uunet.UU.NET (c.s.misc)
roy@phri.UUCP (Roy Smith) (09/23/89)
In <1989Sep23.010904.7650@NCoast.ORG> allbery@ncoast.ORG (Brandon S. Allbery): > He [i.e. me] was insulting only to the person who claimed to the original > poster that the memory speeds *had* to match. [...] There is, by and large, > only *one* case where the memory speeds would have to match: if the memory > storage system accesses more than one memory chip at the same time, all of > those chips must be the same speed or the memory access hardware will get a > severe case of heartburn. Again, bullshit. OK folks, let's go over this slowly. When a RAM chip is is given a speed rating, what that means is the *minimum* amount of time it takes for the chip to make sure that the data being presented on its output data pin(s) is stable and valid. It holds it there for as long as the address and stobe signals stay constant. Follow this example. You're a memory controller, I'm a ram chip. You are designed to operate with 120ns chips. I claim to be such a 120ns chip. You give me an address and tell me that you want to access that address for reading. Then you say "OK, start NOW!" I putter around inside, pull out the data, and put it on my output pin. Since I promise 120ns access time, sometime within 120ns after you said "NOW", I've got that data ready for you, and I'll hold it there waiting for you until you tell me I can let go. Since you're designed for 120ns chips, you probably wait about 125ns, read the data I've presented, and tell me you've got it. Now, imagine I'm a 100ns (or 80ns, or whatever, as long as it's less than 120ns) chip. You tell me what you want and say "START NOW". Since I'm promising 100ns read times, I make sure I get that data to you in 100ns. Since you're a 120ns controller (with the same built-in 5ns timing error margin), you grab the data 125ns after you said "NOW". I had it ready at 100ns, but no problem, I'm perfectly willing to sit and twiddle my thumbs for 25ns until you get your act together, read the data pin, and tell me you've got it. In fact, you don't even *know* I'm a 100ns chip. All you know is that you demand I be ready in 120ns or less, and couldn't care (and wouldn't notice) if that means 119.5ns or 65ns. Just don't let it be 121ns or we might be in trouble (actually, since you're willing to allow an extra 5ns slop, I'll probably get away with 121ns, but not 126ns). OK, now imagine you're doing 32-bit wide transfers. Me and my three brothers are all lined up side by side (in this case, one "brother" is actually 8 chips on a SIMM, but the same argument could hold for chips within a SIMM). I'm a 120ns SIMM, two of my brothers are 100ns SIMMs, and the other brother is a 80ns SIMM. You give us all the address information and say "NOW". sometime before 80ns is up, the guy on the end has his data ready and starts twiddling his thumbs. Sometime in the next 20ns, the two guys in the middle get their act together and go into thumb-twiddling mode. Eventually, sometime before 120ns has elapsed from when you said "NOW", I'm ready. At 125ns, just like always, you grab the data we've got ready waiting for you. You don't know if that data has been read for 5ns or 45ns (in fact, some of it has been ready for the former, some for the latter, and some inbetween). Once you've got it, you tell us all your're done with us, and we go do whatever it is dram chips do when they are not being accessed (dribbling little bits of charge on the floor, I guess). No mess, no fuss, no memory heartburn. You may have wasted some money on chips that were faster than you needed (or could use), but you won't have any memory problems. -- Roy Smith, Public Health Research Institute 455 First Avenue, New York, NY 10016 {att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu "The connector is the network"
jtw@lcs.mit.edu (John Wroclawski) (09/24/89)
In article <1989Sep23.010904.7650@NCoast.ORG> allbery@NCoast.ORG (Brandon S. Allbery) writes:
There is, by and large, only *one* case where the memory speeds would
have to match: if the memory storage system accesses more than one
memory chip at the same time, all of those chips must be the same
speed or the memory access hardware will get a severe case of
heartburn....
Jees, everybody's -so- confused.
The main memory system of the Mac is a simple clocked design with
completely fixed timing. What this means is that the SIMMs must
produce data X time after they are asked. Period. It doesn't matter if
they do it faster than that, and it doesn't matter if they do it at
different speeds, as long as the data is ready when the CPU needs it.
Perhaps this nonsense about needing the same speed for all the SIMMs
in a bank got started because the -size- of all the SIMMs in a bank
must be the same. Who knows.
John T. Wroclawski - MIT Lab for Computer Science - jtw@lcs.mit.edudwells@Apple.COM (Dave Wells) (09/24/89)
In article <11900@polya.Stanford.EDU> kaufman@Neon.Stanford.EDU (Marc T. Kaufman) writes: >I rise to Roy Smith's defense. That IS a constructive comment -- to the >effect that: the folklore that says you can't mix memory speeds (subject to >the requirement that each memory module is itself adequately fast) -- is >Bullshit. > >Now I know that one doesn't have to be an EE to own and operate a computer. >But we don't have to be afraid of them, either. There is a lot of tolerance >in the design of a computer just so spot shortages of a particular chip, or >a low-tolerance part, won't make the machine unbuildable. That's why so many >(IBM) clone makers can push nominal 16 MHz machines to 20MHz -- as long as >you don't get them too hot. > >If you want to cause trouble, why don't we start the rumor that using faster >memory chips will invalidate the FCC clearance because the faster rise times >radiate more... It is possible for mixed speed RAM in a bank to cause malfunctions. In a former life I was in tech support for a small accelerator company. While I was there, we discovered that combinations of different speed (and sometimes manufacturer) RAM would cause the Mac to go out to lunch. This wasn't a one time incident, and all of the RAM in use was rated at or above spec. The Mac's would occassionally die when we mixed some brands/speeds of RAM within banks. (Hey, don't worry. I'm not an EE ;-] ) -Dave -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- Dave Wells, Apple Computer, Inc. MS: 37-Y (408) 974-5515 Mail: dwells@apple.com or AppleLink d.wells or GEnie D.WELLS These opinions may be nothing more than the ramblings of a fatigued tinkerer -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
allbery@NCoast.ORG (Brandon S. Allbery) (09/24/89)
As quoted from <4007@phri.UUCP> by roy@phri.UUCP (Roy Smith): +--------------- | In <1989Sep23.010904.7650@NCoast.ORG> allbery@ncoast.ORG (Brandon S. Allbery): | > He [i.e. me] was insulting only to the person who claimed to the original | > poster that the memory speeds *had* to match. [...] There is, by and large, | > only *one* case where the memory speeds would have to match: if the memory | > storage system accesses more than one memory chip at the same time, all of | > those chips must be the same speed or the memory access hardware will get a | > severe case of heartburn. | | Again, bullshit. OK folks, let's go over this slowly. When a RAM +--------------- All I can offer in extenuation is that this *was* the case at the time when I got my knowledge. However -- the computer in question had memory-management hardware that was consistently riding the very edge of the capabilities of the chips involved, including memory and address-translation circuits, etc., and in fact one memory chip that was "in spec" caused the memory management hardware to do weird things. The chip was then tested in another computer and it worked fine; and its replacement in the first computer also worked fine. Perhaps the moral for all should be "don't take computer hardware for granted." ++Brandon -- Brandon S. Allbery, moderator of comp.sources.misc allbery@NCoast.ORG uunet!hal.cwru.edu!ncoast!allbery ncoast!allbery@hal.cwru.edu bsa@telotech.uucp, 161-7070 BALLBERY (MCI), ALLBERY (Delphi), B.ALLBERY (GEnie) Is that enough addresses for you? no? then: allbery@uunet.UU.NET (c.s.misc)
pfluegerm@valley.UUCP (Mike Pflueger) (09/25/89)
In article <34977@apple.Apple.COM>, dwells@Apple.COM (Dave Wells) writes: > In article <11900@polya.Stanford.EDU> kaufman@Neon.Stanford.EDU (Marc T. Kaufman) writes: > >I rise to Roy Smith's defense. That IS a constructive comment -- to the > >effect that: the folklore that says you can't mix memory speeds (subject to > >the requirement that each memory module is itself adequately fast) -- is > >Bullshit. > > > >Now I know that one doesn't have to be an EE to own and operate a computer. > >But we don't have to be afraid of them, either. There is a lot of tolerance > >in the design of a computer just so spot shortages of a particular chip, or > >a low-tolerance part, won't make the machine unbuildable. That's why so many > >(IBM) clone makers can push nominal 16 MHz machines to 20MHz -- as long as > >you don't get them too hot. [some stuff deleted] > It is possible for mixed speed RAM in a bank to cause malfunctions. In a > former life I was in tech support for a small accelerator company. While > I was there, we discovered that combinations of different speed (and sometimes > manufacturer) RAM would cause the Mac to go out to lunch. This wasn't a > one time incident, and all of the RAM in use was rated at or above spec. The > Mac's would occassionally die when we mixed some brands/speeds of RAM within > banks. (Hey, don't worry. I'm not an EE ;-] ) Well, I *AM* an EE, and the way this memory is being used, there should be no problem mixing it. In fact, even though all chips on a SIMM are marked with some speed, in real life they vary - the speed indicated is the guaranteed MAXIMUM access time. Even if you use 150nS SIMMs with 40nS SIMMs, there is no problem - if the CPU hardware is designed for 150nS memory. This is because the CPU puts out its read (or write) request on the bus, which is in turn received by the 150nS and 40nS memory simultaneously. The CPU then waits for the data to be available. If it was designed for 150nS, its going to wait 150nS. If some faster memory makes data available sooner (e.g. 40nS), it doesn't matter because the CPU is waiting for a "fixed" 150nS. CPU's generally have a "wait" line which essentially halts the processor while slower peripherals (such as memory) get their data on the bus. Hardware external to the CPU (a divider) holds this wait line for some number of clock cycles ("wait states") to do this. It is usually fixed in hardware. I suspect Dave's experience with RAM problems were due to some other problem, maybe due to the Mac (Plus, II) borderline power supply designs/poor cooling. I have heard of higher power RAM causing problems due to power supply overload and overheating, especially in the Mac Plus. And if this was on an accelerator board, this would only aggravate the problem. I recommend a fan to prolong the life of your Plus. Hope this clears this issue up. -- Mike Pflueger @ AG Communication Systems (formerly GTE Comm. Sys.), Phoenix, AZ UUCP: {...!ames!ncar!noao!asuvax | uunet!zardoz!hrc | att}!gtephx!pfluegerm Work: 602-582-7049 FAX: 602-581-4850 Packet: WD8KPZ @ W1FJI
straka@cbnewsc.ATT.COM (richard.j.straka) (09/27/89)
In article <45d9e852.15840@valley.UUCP| pfluegerm@valley.UUCP (Mike Pflueger) writes: |In article <34977@apple.Apple.COM|, dwells@Apple.COM (Dave Wells) writes: || In article <11900@polya.Stanford.EDU| kaufman@Neon.Stanford.EDU (Marc T. Kaufman) writes: || |effect that: the folklore that says you can't mix memory speeds (subject to || |the requirement that each memory module is itself adequately fast) -- is || |Bullshit. |Even if you use 150nS SIMMs with 40nS SIMMs, there is no problem - if the CPU |hardware is designed for 150nS memory. This is because the CPU puts out its |I suspect Dave's experience with RAM problems were due to some other problem, |maybe due to the Mac (Plus, II) borderline power supply designs/poor cooling. Yes, the statement immediately above may very well be true since faster RAMs (less nS) takes more power supply current. Given the same manufacturer and process, variations naturally occur in speed and power, which are inversely related. Across manufacturers and processes, all bets are off; you have to look at the spec sheets. But even then, that does not always tell all, since they tell you the MAX power and MAX access times. The bright side on this topic: It's probably a tertiary level effect. I, for one, even with a plus would not worry about 80 nS RAM in my machine. PS: Yes the basic argument is true: almost all memory systems are synchronous at some hardware level. This means that you can mix speeds below that level as long as you satisfy the basic max access time specs. -- Rich Straka att!ihlpf!straka MSDOS: All the wonderfully arcane syntax of UNIX(R), but without the power.