jk@duke.UUCP (Judd Knott) (02/26/85)
At a recent VLSI workshop there was some talk of an attempt at wafer-scale integration at Trilogy. I received this information second hand and I am extremely interested in any information concerning this (or other) wafer- scale projects. In particular I am interested in the yield, the number, causes, and distribution of defects, the technology and feature size of the project, and what kind of (if any) fault-tolerant techniques were introduced to enhance the yield. The information about Trilogy's project was rather sketchy; all I heard was that yield was 0%. I know that data concerning process and yield is not circulated indiscriminately, but I would be more than willing to sign non-disclosure agreements for anyone willing to enlighten me. My research is in fault-tolerant design methodologies for wafer-scale VLSI parallel processing arrays. My only knowledge of yield statistics is what is reported in the literature in the form of vague and unsubstantiated proclamations. Your assistance will be greatly appreciated. Thank You. Judson D. Knott Duke University Department of Computer Science Durham, NC 27707 (919) 684-5110 ext: 26 duke!jk