larryh@tekgvs.LABS.TEK.COM (Larry Hutchinson) (10/14/89)
The clock speed of the ci is 55% faster than the IIcx. This combined with the support of burst mode cache refill would lead me to expect that the ci should be at least 60% faster on compute bound applications. Everything I have seen in the literature indicates the ci is only 35 to 40% faster. Addition of a $1000 external cache board boosts the speed up to ~60% faster than a cx. Since the memory speed requirements paralleled the clock speed change, I had hoped that the number of memory wait states had not changed. My understanding is that the cx runs one wait state (4 clock asynchronous read). It would appear that the ci is running with two wait states. Questions: 1. Anybody actually know how many wait states the ci is running? 2. How does the nExt box compare? 3. Are the benchmarks being run properly? 4. Are the benchmarks being run while the machine is using the internal 8 bit color display? Does this slow down the machine? P.S. A quick look at the 68030 data sheet indicates that a 4 clock asynchronous read would require ~110ns system access time. 80ns rams thus give 30ns for skews and buffer delays. Seems do-able to me. What was the problem? Did the designers only have access to design tools available on the Mac :-) Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077 UUCP: [uunet|ucbvax|decvax|hplabs]!tektronix!tekgvs!larryh ARPA: larryh%tekgvs.LABS.TEK.COM@RELAY.CS.NET CSNet: larryh@tekgvs.LABS.TEK.COM