jklee@phoenix.Princeton.EDU (James Kin Wah Lee) (10/06/89)
A little while back, someone posted a question regarding the RAM chips in the IIci. More recently in MacWeek, they mention that the IIci contains "special, 80 nanosecond, fast page mode" RAM chips. I have been following the news but I have not seen any postings regarding these chips. What are "fast page mode" SIMMs and how are they different from "normal" SIMMs? Is one obligated to use only these special SIMMs in the IIci? More importantly, can one obtain these from the vendors who advertise in MacWeek for the same prices as "normal" SIMMs??? Any info would be appreciated. JIM -------------------------------------------------------------------------- Jim Lee (jklee@phoenix.Princeton.EDU) * * * * * * * * * * * * * * * * * Dept. of Geol. & Geophys. Sci. * THERE ARE STRANGE THINGS DONE * Princeton University * IN THE MIDNIGHT SUN ..... * Princeton, NJ 08544 * * * * * * * * * * * * * * * * * --------------------------------------------------------------------------
jstewart@rodan.acs.syr.edu (Ace Stewart [Jonathan III]) (10/07/89)
In article <10730@phoenix.Princeton.EDU> jklee@phoenix.Princeton.EDU (James Kin Wah Lee) writes: >What are "fast page mode" SIMMs and how are they different from >"normal" SIMMs? Is one obligated to use only these special SIMMs >in the IIci? More importantly, can one >obtain these from the vendors who advertise in MacWeek for >the same prices as "normal" SIMMs??? Hokay, having recently (ie this morning) talked with a Systems Engineer from Apple, here is the scope as seen through my eyes from his words. The 80ns are rather unique. They can be standard memory chips in that they run 80ns, but there is a difference in how they perform in connection to the CPU. The IIci has what is called page-burst mode. It can take multiple commands per cycle, and this is what is unusual. The fact that this occurs allows for nothing to do with the SIMMS itself, so therefore they are standard 80ns chips. However, Apple is offering an extended SIMMS chip that has a parity check sequencer on it. For those of you familiar with parity, you will realize that a parity error occurs rather infrequently, and the S.E. I spoke with was quoted as saying on the average of 7 years. This is a chip that must be bought directly through Apple itself, and has its' biggest sales through government institutions. Not something the normal person would need.... Does this help at all? Ace -- | Ace Stewart (Jonathan III) |A /\ | | Affiliation: Eastman Kodak Company. Rochester New York | _/ \_ | | Internet/ARPA: jstewart@rodan.acs.syr.edu | \_ _/ | | Bitnet: jstewart@sunrise.bitnet | /\ A|
marc@Apple.COM (Mark Dawson) (10/07/89)
In article <10730@phoenix.Princeton.EDU> jklee@phoenix.Princeton.EDU (James Kin Wah Lee) writes: >A little while back, someone posted a question regarding the >RAM chips in the IIci. More recently in MacWeek, they mention that >the IIci contains "special, 80 nanosecond, fast page mode" RAM >chips. I have been following the news but I have not seen any >postings regarding these chips. > >What are "fast page mode" SIMMs and how are they different from >"normal" SIMMs? Is one obligated to use only these special SIMMs >in the IIci? More importantly, can one >obtain these from the vendors who advertise in MacWeek for >the same prices as "normal" SIMMs??? > (1) You can use 80ns "regular" SIMMs, *BUT* at room temperature they may work only for a while, almost certainly failing eventually as the Mac warmed up. It's similar to using slower RAM in general. Since there is often considerable margin in the RAM spec, they may actually present valid data in time, but aren't likely to work across the full temperature range. So...you may be able to get 80ns "regular" SIMMs to work for a while, but it is highly unlikely they will continue to work while in your machine. One other note: at our local electronics shops (Fry's), almost all of the 1meg 80ns SIMMs sold ARE fast-page mode...its pretty hard to find 80ns "regular" SIMMs. (2) As I understand it, a 1 meg chip only has 10 address lines, but you need 20 bits to address the full 1 meg. So what you do (for a read) is to put the low 10 bits of the address on the address lines, and strobe the CAS line. You then but the upper 10 bits of the address on the address lines, and strobe the RAS line. Now you have given the chip the "full" address, and it will output the data you want. For a "regular" chip, you must do this (CAS-RAS) to read each piece of data. A fast page mode chip, however, doesn't have to do this full cycle each time. You need to start off the same CAS-RAS cycle the same way, but the next 3 reads you do, all you need to do is to put the upper 10 bits of data address on the address lines, and strobe the RAS line (this, of course, means you have to be reading datum that have their lower 10 bits of addresses the same). Thus you need 4 operations to get the 1st piece out, but only 2 operations (putting data on address lines, strobe CAS) to read the next three pieces of data. The reason I gave the "read" example is that the 68030 (which the IIci uses) only suppports burst reads, not writes. It does 4 longword burst reads to load the cache line. Without burst mode, (using the data cache) it would require 5 cycles for every read. With burst mode, it can read the first longword in 5 clock cycles, and the other 3 longwords in that quad-longword-aligned block in 2 clock cycles each, to fill the cache line (hence 5/2/2/2 bursting). Hope this was the info you wanted (and its not too long-winded). Mark
noah@Apple.COM (Noah Price) (10/09/89)
Just a minor correction... In article <35341@apple.Apple.COM> marc@Apple.COM (Mark Dawson) writes: >(2) As I understand it, a 1 meg chip only has 10 address lines, but you need >20 bits to address the full 1 meg. So what you do (for a read) is to put the >low 10 bits of the address on the address lines, and strobe the CAS line. You ^^^^^^^^^^^--not really, but ok in theory RAS~--^^^ >then but the upper 10 bits of the address on the address lines, and strobe the ^^^^^^^^^^^^^--again, not really >RAS line. Now you have given the chip the "full" address, and it will output ^^^--CAS~ >the data you want. So, RAS~ is asserted first with the address of the row, followed by CAS~ with the address of the column within that row. CAS~ can be asserted repeatedly to get other columns from that row. noah price Mac IIci Hardware Design Team Apple Computer, Inc. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ noah@apple.com ...!{sun,decwrl}!apple!noah
daveh@cbmvax.UUCP (Dave Haynie) (10/10/89)
>What are "fast page mode" SIMMs and how are they different from >"normal" SIMMs? Is one obligated to use only these special SIMMs >in the IIci? More importantly, can one >obtain these from the vendors who advertise in MacWeek for >the same prices as "normal" SIMMs??? "Fast-Page" is one particular special DRAM mode, and these days by far the most common. Set the way-back machine for about the mid 80s or so. Back then, most DRAM had a special mode called "page" mode. Normally, a DRAM requires two address cycles, a row address, supplying 1/2 the address information, followed by a column address, supplying the other 1/2 of the address. They figured if they allowed the row address to stay latched in the part, multiple column addresses could be supplied to access all the memory in that "page". And since you now only had to wait that column access time, not the row access time, accesses to a page could be much faster. Only, originally they weren't that much faster. Then they started to see how useful such a mode could be, and specificially work on cutting down the column access time. Now you have fast-page mode, which gives you a normal row access time but a relatively fast column access time. Nearly every 1 megabit density DRAM with page mode has fast-page mode, but a few of the early ones (usually NMOS rather than CMOS) didn't. I don't know just what they've packaged on SIMMs these days. The other thing to watch for are the other types of DRAM. Along the way, two other fast access modes were invented. Static Column mode works much like fast-page mode, only the column addresses aren't latched, they work much more like the addresses presented to static RAMs. This is nice if you're designing with that in mind, since you don't have to worry about supplying an exact CAS signal, but if your addresses don't remain valid for the whole memory cycle, this can be a problem. The other speedup mechanism is called nybble mode. Here, you get 4 bits available internally from each DRAM, and they are shifted out in a rotating order, but much faster than for SC RAMs or FP RAMs. Interestingly, the nybble mode RAM exactly matches the way '030 burst mode works; the only problem is size -- for a 32 bit bus, you need a minimum of 4 megabytes of RAM using nybble mode parts (they're only in 1 bit wide configurations). Both nybble and SCRAMs are available in SIMM packages, but you _usually_ have to ask for them, and SCRAMs can cause problems in systems that count on a latched column address. > Mark -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
lsanner@dfmp1.UUCP (Lou Sanner M.D.) (10/16/89)
I am getting a IIci soon (hopefully) and I am trying to clarify three memory
questions:
1) Are the configuration rules for the IIci RAM banks DIFFERENT from the other
Mac 68030 machines? According to the Byte review, the IIci does not require
contiguous memory installation. Does this mean that I can mix and move memory
around in the 8 SIMM slots? Can I have a 3MB machine? Can I have two 1MB
SIMMS in the A bank and 2 in the B bank? On the other 68030 machines the
allowable memory configurations are 1-4-5-8 MB given the rules that "bank A
must be filled", "bank B must contain 0 or 4 SIMMs" and "bank A must contain
equal or higher density SIMMs than those in bank B". What are the rules for
the IIci?
2) Will the IIci run more efficiently (faster) under Multifinder if I put
"some" RAM in the A bank and "most" in the B bank. According to the Byte
review the video system locks out the CPU access to the A bank for 600ms when
it refreshes. Apparently Multifinder loads applications in the B bank first
so these would not be slowed by this recurrent lockout. What about when
System 7 comes along - where should memory be then?
3) Do I have to put 80ns RAM in the IIci? We have a (growing) bunch of 120ns
and 150ns 256K SIMMs here. I suspect that I do have to use 80ns RAM... so
where is a good source (price, reliability...)?
Please e-mail me directly with any comments/answers in addition to posting
them. Slogging thru this news section is too time consuming.
--- Lou Sanner MD, MSPH --- DFMP, 777 S. Mills St., Madison, WI 53715
(608) 263-1731 dfmp1!lsanner@schaefer.math.wisc.edu
:emarc@Apple.COM (Mark Dawson) (10/16/89)
In article <112@dfmp1.UUCP> lsanner@dfmp1 (Lou Sanner M.D.) writes: > >I am getting a IIci soon (hopefully) and I am trying to clarify three memory >questions: > >1) Are the configuration rules for the IIci RAM banks DIFFERENT from the other >Mac 68030 machines? According to the Byte review, the IIci does not require >contiguous memory installation. Does this mean that I can mix and move memory >around in the 8 SIMM slots? Can I have a 3MB machine? Can I have two 1MB >SIMMS in the A bank and 2 in the B bank? On the other 68030 machines the >allowable memory configurations are 1-4-5-8 MB given the rules that "bank A >must be filled", "bank B must contain 0 or 4 SIMMs" and "bank A must contain >equal or higher density SIMMs than those in bank B". What are the rules for >the IIci? > The only rule change between the IIcx && the IIci is that the IIci allows you (and I would recommend) to put more memory in bank B than in bank A. You still can only have 1, 4, 16, or 64mb in a bank (not 3mb, etc). You can also leave bank A empty (you would need to use a video card if you did this, though). >2) Will the IIci run more efficiently (faster) under Multifinder if I put >"some" RAM in the A bank and "most" in the B bank. According to the Byte >review the video system locks out the CPU access to the A bank for 600ms when >it refreshes. Apparently Multifinder loads applications in the B bank first >so these would not be slowed by this recurrent lockout. What about when >System 7 comes along - where should memory be then? > Yes. The built-in-video runs out of bank A. If there is memory in bank B also, the IIci puts all programs, etc in bank B. When you have used up all the memory in bank B, the IIci starts using the memory that the built-in video hasn't used. So if you use MacsBug/TMON and look at address 0, you're really looking at the 1st part of bank B. Note that this is done in the hardware, not the system software...system 7 should act just like any other application--loading into bank B first. Anytime your program uses or access bank A while built-in video is running, it will be slowed down (I'm not sure by how much). My current configuration is 4mb in bank B, and 1mb in bank A. The addressing looks something like: bank B Bank A |xx 0|//|yy xx+1| video RAM | >3) Do I have to put 80ns RAM in the IIci? We have a (growing) bunch of 120ns >and 150ns 256K SIMMs here. I suspect that I do have to use 80ns RAM... so >where is a good source (price, reliability...)? > You need to put 80ns FAST-PAGED RAM in the IIci (there have been some earlier articles on that). Anything else will not work (or not work for long). Mark