2HGXDISC@kuhub.cc.ukans.edu (11/17/89)
re: mac memory
As long as you follow the 'row' law for memory, there should be no problems.
In other words, 2 lines of memory sockets make up a row. Each row must have
the same speed memory chips in it. The faster chips must be towards the center
or the mother board.
(compliments MacZone)spraggs@ve7apu.uucp (John Spraggs - VE7ADE) (11/17/89)
In article <18210@kuhub.cc.ukans.edu> 2HGXDISC@kuhub.cc.ukans.edu writes: >re: mac memory >As long as you follow the 'row' law for memory, there should be no problems. >In other words, 2 lines of memory sockets make up a row. Each row must have >the same speed memory chips in it. The faster chips must be towards the center >or the mother board. > (compliments MacZone) Every time I see an explanation like this I have to wonder. The first order approximation has to be that there is no reason why mixing chips with different speed markings will cause a problem. If the hardware design has not been messed up to the point of not working with the faster parts in the first place, then mixing shouldn't make any difference. Nothing says that the manufacturer has to ensure that all parts marked as 150 ns are not faster than 120 nsec. At a particular stage in the learning curve for a given mask design, the manufacturer may have to run through a significant fraction of his production to find the fraction that do not fail the premium speed test threshold. Later when the yield has improved to the point that all parts pass at that value, he will still mark some at the slower number because that portion of his market is price, not performance sensitive. If you are cheap and willing to gamble, you can bet that this is the case and use these parts where they are not guaranteed to work. If you put in faster parts than required, no harm should be done, except to your pocketbook if cheaper parts were available. By spending more, you might be buying an insignificant increase in reliability or you might someday want to take them out of your future dinosaur and put them in a machine that needs the speed. What you can't do is mix sizes in the same row. The 68000 is a 16 bit machine and accesses 2 SIMMs at a time, while the 68020 and 68030 are 32 bit and everything applies to 4 SIMMs. This must be where the mistake in the above information was derived. Surely this is one of the novice questions that 'they' were going to figure out how to distribute so as to reduce the bandwidth taken. :+( John Spraggs van-bc!ve7apu!ve7ade!spraggs