FXDDR@ALASKA.BITNET (03/01/88)
Well, give credit where it is due. After all the grouching about Atari, here's something positive. After calling around trying to get information about bus timing in the ST and getting nowhere, I mailed a request to Cindy Claveran and just got an 8-page document called "Mega ST Series Internal Expansion Bus Documentation" dated 2 October 1987. It doesn't have timing diagrams but it does have some interesting tidbits, for example "Atari has set aside the addresses C00000 through CFFFFF, FF0000 through FF7FFF, and FFFE00 through FFFFFD for use by outside developers." Nice to know, since my pet project just fits in 7FFF, and I was going to arbitrarily stick it at 400000. I still don't know how much time GLUE and MMU eat out of the available access time or what the DMA chip timing looks like, but I guess I can just assume RAM faster than 150ns will work. We'll see what happens. There's always the logic analyzer and other medieval tools of torture. With memory getting expensive, perhaps instead of an external RAM disk an internal RAM disk in the C00000-CFFFFF slot would be more attractive...all that would take is the RAM and a DRAM controller. I wonder why Atari gives such a small amount of address space to developers. They barely use 5 of the 16 MB now. Do they really need to reserve 10 MB of space for their own future use? Oh well..."I got mine." Don Rice FXDDR@ALASKA.bitnet