wzg91@TTACS1.TTU.EDU ("BROWN, KEVIN") (04/23/89)
The 68000 does not take 4 clock cycles per instruction. It actually takes 4 clock cycles per memory hit, assuming no wait states. To get the number of clock cycles per instruction you have to take into account the average number of clock cycles used for actual instruction execution. According to the MC68000 manual, a memory read cycle has the following steps (A * after a signal implies an active low signal): 1. The CPU does the following: (a) Sets R/W* to Read (R/W* high) (b) Places function code on FC0-FC2 (only important for MMUs which differentiate between User and Supervisor states, and Program and Data segments). (c) Places address on A1-A23. Note that A0 is not present. Instead, UDS* (Upper Data Strobe) and LDS* (Lower Data Strobe) are asserted appropriately to tell the memory management circuitry which byte(s) (lower, upper, or both) are to be read by the CPU. (d) Asserts Address Strobe (AS*) (e) Asserts UDS* and LDS* 2. In response, the memory circuitry does the following: (a) Decodes the address (b) Places the data on D0-D15 (c) Asserts Data Transfer Acknowledge (DTACK*) 3. The CPU then: (a) Latches the data on D0-D15 (b) Negates UDS* and LDS* (c) Negates AS* 4. The memory circuitry then: (a) Removes the data from D0-D15 (by tri-stating the bus transceivers) (b) Negates DTACK* According to the Motorola specs, the data on the bus must be valid 1/2 clock cycle before it is latched by the falling edge of the clock (2 falling edges after DTACK* is asserted). Note that DTACK* may actually be asserted before the data is valid, provided that the data is valid no more than 1-1/2 clock cycles later. This gives the memory circuitry 1-1/2 clock cycles to decode the address and make the data valid on the bus. That's 187.5 ns. The write cycle gives you only one clock cycle between the assertion of AS* and the time that DTACK* needs to be asserted for the memory circuitry to decode the address and to latch the data. However, a perfectly acceptable solution to this is to latch the data in some fast buffers and then actually perform the write to memory AFTER asserting DTACK*, since the actual memory cycle takes 4 clock cycles. This leaves (according to the timing diagrams) 1 clock cycle to actually complete the write after the assertion of DTACK*. Thus, the Atari ST does not use any wait states for its memory accesses. Kevin Brown Internet: wzg91@ttacs1.ttu.edu or c8u00@ttacs1.ttu.edu Bitnet: WZG91@TTACS1 or C8U00@TTACS1 Snail: 404 Gaston Hall Texas Tech University Lubbock, TX 79406 Voice: (806)742-4375 Disclaimer? I don't need any disclaimer! Everything I say is right...:-)