logajan@ns.network.com (John Logajan) (03/04/90)
Yet another memory upgrade procedure (old style 520 ST to 2.5 meg)
I was running out of room with my EZRAM 1 meg upgrade, and it was
starting to act flaky (it would wiggle loose from the MMU socket.)
So I sent away for some 1Mbit DRAMS from Microprocessors Unlimited
Inc.; 24000 S. Peoria Ave; Beggs Oklahoma 74421 (918) 267-4961
for $8.75 each (February 24, 1990 prices.) They sent me 16
Samsung KM41C1000AP-8 DRAMS. Total price $140.00 plus $7.40 for
Federal Express delivery = $147.40 -- the fastest delivery of
any mail order parts I've ever sent for and received! (Of course,
I gave them a credit card number.)
I removed the old EZRAM upgrade -- no need for it anymore.
Then I bent up pins 1,2,3,4,5,15,16,17,18 of each new DRAM so that
they pointed out sideways and clipped off all but about 1/16 inch
of the pins.
Next I soldered short wires on each of the on-board old DRAM pins
2 and 16. The old DRAM pin 2 wire would later be connected to the
bent up pins on the new DRAM, pins 1 and 17 (data I/O) while the
wire to old pin 16 would be connected to new pin 18 (ground.) I
did these wires first because they would be hard to get at after
you piggy back the new DRAMS on top of the old DRAMS.
Now I piggybacked all the new DRAMS on top of the old 520 ST
DRAMS. The new DRAMS have an extra set of pins, so you line them
up such that pin 9 of the new DRAM is on top of pin 8 of the old
DRAM -- as shown below.
[=== 1] [18===]
[=== 2] ( 1) (16) [17===]
[=== 3] ( 2) (15) [16===]
[=== 4] ( 3) (14) [15===]
[=== 5] ( 4) (13)-[14] Piggybacked view.
[ 6]-( 5) (12)-[13]
[ 7]-( 6) (11)-[12]
[ 8]-( 7) (10)-[11]
[ 9]-( 8) ( 9)-[10]
As you can see 6,5 7,6 8,7 9,8 10,9 11,10 12,11 13,12 and
14,13 pins are soldered together.
[=== 1] Din GND [18===]
[=== 2] WRT Dout [17===]
[=== 3] RAS CAS [16===]
[=== 4] N.C. A9 [15===]
[=== 5] A8 A6 [14] 1Mbit DRAM Pinout
[ 6] A0 A3 [13]
[ 7] A2 A4 [12]
[ 8] A1 A5 [11]
[ 9] PWR A7 [10]
( 1) A8 GND (16)
( 2) Din CAS (15)
( 3) WRT Dout (14)
( 4) RAS A6 (13) 256K DRAM Pinout
( 5) A0 A3 (12)
( 6) A2 A4 (11)
( 7) A1 A5 (10)
( 8) PWR A7 ( 9)
Now for the tedious wiring job.
Connect each of the wires on old DRAM pin 2 to new DRAM pins 1 and 17.
Connect each of the wires on old DRAM pin 16 to new DRAM pin 18.
From any old-DRAM pin 3, daisy chain a wire to each new DRAM pin 2.
From any old-DRAM pin 1, daisy chain a wire to each new DRAM pin 5.
Now find the MMU socket. Pin numbering (top view) goes like this:
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 / < > M 60
11 A 59
12 D 58
13 9 57
14 56
15 55
16 MMU CHIP 54
17 (top view) 53
18 RAS1 C025912-38 52
19 U15? 51
20 50
21 CAS1L 49
22 CAS1H 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
You need to connect pin 18 of the MMU to each of the new DRAM pins 3.
You need to connect pin 64 of the MMU to a 33 ohm resistor.
Connect the other side of the resistor to each of the new DRAM
pins 15.
You need to connect pin 21 of the MMU to ONLY eight of the new
DRAM pins 16 (the low order byte, chips U16, U17, U18, U24, U25,
U28, U29, U30 -- on the old style 520 ST.)
You need to connect pin 22 of the MMU to the OTHER eight new DRAM
pins 16 (the high order byte, chips U32, U33, U34, U38, U42, U43,
U44, U45 -- on the old style 520 ST.)
That should do it. TOS 1.4 figures out the size of the RAM space
available and automagically configures the MMU to supply the
correct RAS and CAS signals etc for 2.5 meg that you now have.
--
- John Logajan @ Network Systems; 7600 Boone Ave; Brooklyn Park, MN 55428
- logajan@ns.network.com, john@logajan.mn.org, 612-424-4888, Fax 424-2853