jeroen@plato.phil.ruu.nl (Jeroen Scheerder) (07/24/90)
In article <1990Jul23.135351.4486@diku.dk>, jensting@rimfaxe.diku.dk (Jens Tingleerd writes: |>jeroen@plato.phil.ruu.nl (Jeroen Scheerder) writes: |> |>>In article <5223@castle.ed.ac.uk>, tj@castle.ed.ac.uk (T Jones) writes: |>[..] |>>I was the one posting about the 3.0 Mb modification; however, having read the explaining it all (it's from a German magazine, I think it's |>>called 'ST Magazin' or something) I decided I would let someone more experien work for me. |>>Looking in my computer I see 2 SIMMs, and a *LOT* of wire. |> |>I, for one, doubt that you are *at all* able to make the ST use 3.0 MB. There |>are two banks of memory, each wth either 0.5 MB or 2.0MB. That makes |> |> 0.5 MB 1x0.5 |> 1.0 MB 2x0.5 |> 2.0 MB 1x2.0 |> 2.5 MB 1x0.5 + 1x2.0 Not available from Atari ... |> 4.0 MB 2x2.0 |> |>The above calculation is based on the fact that the MMU knows about |>two banks, NO MORE. the nice thing ( ;-) ) is that the MMU autodetects.. . |> |>So, no unused 0.5 MB in a 2.5MB installation, no 3.0 MB installation |>possible. |> |>Disclaimer |> This may not be true for STEs, I don't know.. . |> Do correct me if I'm wrong. |> |>*IF* I'm wrong, please give a reference to the relevant article.. . |>(I have seen ads for 5.0MB extensions, where the last 1 MB was |>used for RAM disk, so perhaps....) |> |> Jens |>Jens Tingleff MSc EE, Institute of Computer Science, Copenhagen University |>Snail mail: DIKU Universitetsparken 1 DK2100 KBH O |>"It never runs around here; it just comes crashing down" |> apologies to Dire Straits Yes - you *ARE* wrong. First: 2.5 Mb is *NO* *PROBLEM* *AT* *ALL*. Like you say, 0.5-Mb bank go nicely together. The mere fact that Atari ships no 2.5 Mb-equippe " this configuration impossible. 3.0 Mb is possible too; but it really is a hack to get around the 2 bank limit. I will describe that in the following article. The following stuff really should be put in the 'tech' newsgroup, but I started request to Dave Small ... anyway, here it is. My ST *DEFINITIVELY* has 3.0 Mb. I agree, not long ago I thought this impossible the magazine "ST Computer" 3/1990 (a German magazine), the author K. D. Litteck describes how it is done (the article is called "Aus zwei und ein halb m German, and my German is not too good, but I'll try to describe the article accurately. How does it work? Well after determining memory configuration (see below) TOS st amount of memory it thinks is available. Say you've got 3.0 Mb available (like I do); TOS at first thinks 2 banks of 2 Mb are available and sets out to c then runs into nonexistent memory when it reaches the end of the three available megabytes. En exception occurs of type buserror occurs, at which is de adress the error occurred. This adress is then written in the TOS variable phystop, thus setting the correct memory size. Now TOS boots on ... This works like this in all TOS versions known to mankind. For technical details see part 2 of this posting. "Talking about Math can almost be as satisfying as the real thing, and not half so risky." cf. 'The Bluffer's Guide to Bluffing'
jeroen@plato.phil.ruu.nl (Jeroen Scheerder) (07/24/90)
This is part 2 of an article about ST memory upgrading (technical part). Before getting into the gruesome details, first some general ST memory theory: ST is equipped with Dynamic RAM, and for every memory location a single transist allows for high speed and compact chips. However, the chips need to be refreshed about every 2 millisecs, of which the MMU (among other things) takes care. The DRAMS are bitwise accessed; therefore, the ST adressing in 16 bits, only ban be used. Now the adressing signal is multiplexed (at one adress line two adresses are located, that are consecutively transferred). In DRAM these adresseMx separated. This keeps the number of pins as small as possible. The multiplexing signals is catered for by the MMU too. Now the multiplexing is the reason the DRAMS can only be increased in 4-folds; oing kBit, 256 kBit, 1 MBit and 4 MBit chips currently exist. Two control lines (called RAS and CAS) are of interest (both low-active). RAS tr adress of the multiplexed adress line, CAS the high adress. They work too as chip-selectors. The signal WE selects READ or WRITE mode. Further, the ST divides CAS into CASL and CASH. CASL goes to the chips on adress to 8..15, so that memory can be byte-accessed too. On WORD-read or write both CASL and CASH are active. The ST's MMU can manage two banks of memory. For bank 0 the control lines RAS0, used, bank 1 uses RAS1, CAS1L and CAS1H. These banks can be equipped with 64, 256 or 1024 kBit chips. On coldstart TOS writes patterns in memory and reads them back (all at well-chos determine the memory configuration, and stores in the system variable memconf (a MMU's configuration register ($FF8001) a configuration byte: Bank 0: Bank 1: Value: Total memory: 512 k - $04 0.5 M 512 k 512 k $05 1.0 M 2.0 M - $08 2.0 M 2.0 M 512 k $09 2.5 M 512 k 2.0 M $06 2.5 M 2.0 M 2.0 M $0A 4.0 M (hope I got this right!) On top of all this, MMU also manages to make memory contiguous: allthough the ad bank is 2.0 Mb, in case your bank 0 is 512 k and 1 is 2.0 M the MMU concatenates the total adressing space to a contiguous one (as TOS expects). Now, that's all very well: now we want to fool the MMU to handle up to 5 (!) mem2.0 post a scan of the electronics scheme in MacPaint format (you need it!) We need adress line A9 (not used on 256 kBit chips). It is multiplexed and conta chi adresses A18 and A19. Both NAND-gates serve as OR-gate and should release the D-Latch 1 and 2 when CAS1L or CAS1H become active. An IC 74LS375 demultiplex A9 the adresses A18 and A19. With the D-Latch 3 A18 is obtained, with D-Latch 1 A19. A18 is also led over D-latch 2, being kept until CAS goes high. The IC 74LS139 (2-bit binary decoder) produces with A18, A19, CAS1L and CAS1H ei of which we only need four. These four signals are fed to the memory banks (all formerly 0). Now, some things to pay attention to: - the 2.0 Mb should be bank 0; - the RAS0-line must be broken; - the assignment of RAS- and CAS-lines MUST be corresponding. MMU pin configuration: 6: CAS0H 7: CAS0L 8: RAS0 18: RAS1 21: CAS1L 22: CAS1H 64: A9 Components: - 1 IC 74LS00 - 1 IC 74LS375 - 1 IC 74LS139 - 4 68 Ohm resistors - 1 Block condensator - 1 microFahrad wire or copper litze I hope this is clear enough to you all (once you've seen the picture accompaning "Talking about Math can almost be as satisfying as the real thing, and not half so risky." cf. 'The Bluffer's Guide to Bluffing'