camm@els.ee.man.ac.uk (Ian Camm) (04/05/91)
Hi All, I have just upgraded my 520STe to 2 Megs so I now have 2 1/4M SIMM's rattling about in a draw. A colleague of mine is working on a project at home and could use this RAM. So what I want to know is, what is the pin layout for these SIMM's. If you have the information or can point me in the right direction I would be most grateful. Thanks in advance, Ian -- Ian Camm | JANET: camm@uk.ac.man.ee.els Dept. of Electrical Engineering | ARPA: camm@els.ee.man.ac.uk University of Manchester, England | UUCP: ...!!ukc!man.ee.els!camm Disclaimer: If you think I need one make it up yourself.
baffoni@aludra.usc.edu (Juxtaposer) (04/10/91)
In article <2371@m1.cs.man.ac.uk> camm@els.ee.man.ac.uk (Ian Camm) writes: >Hi All, > >I have just upgraded my 520STe to 2 Megs so I now have 2 1/4M SIMM's rattling >about in a draw. A colleague of mine is working on a project at home and could >use this RAM. So what I want to know is, what is the pin layout for these >SIMM's. I got this from Treavor Peacock somewhere over there in UK: Let me know if it works! ---------------------------------- ____________________ ____________________ | Bank 1 high byte | | Bank 1 low byte | === R90 CAS0HI | CAS1HI and RAS1 | | CAS1LO and RAS1 | === R93 CAS1HI -------------------- -------------------- === R94 CAS1LO -------------------- -------------------- o RAS1 (solder thru) | Bank 0 high byte | | Bank 0 low byte | === R91 CAS0LO | CAS0HI and RAS0 | | CAS0LO and RAS0 | o RAS0 (solder thru) -------------------- -------------------- === A8 === A6 / === A3 9*33ohm--< === A0 \ === A4 === A2 === A5 === A1 === A7 -----------------------front edge of board---------------------------------- The data in/out lines are connected on each chip, so this is the same as on a SIMM, where they are already connected. The data lines are common between bank 0 and bank 1, that is, the data line from the LSB on bank 0 connects to the data line from the LSB of bank 1. SIMM pinouts =-=-=-=-=-=-= PIN# Function. Note '*' means -ve logic. 1 Vcc = +5V 2 *CAS 3 D1 <-- Note, goes from D1 - D8, not D0 - D7. Makes no difference though 4 A0 5 A1 6 D2 7 A2 8 A3 9 Vss = 0V 10 D3 11 A4 12 A5 13 D4 14 A6 15 A7 16 D5 17 A8 18 A9 <-- N/C on 256k SIMMS 19 N/C 20 D6 21 *W 22 Vss = 0V 23 D7 24 *PRD <-- Not on all SIMMS, just pulled low. Best left N/C 25 D8 26 N/C 27 *RAS 28 N/C 29 N/C 30 Vcc = +5V >Thanks in advance, > >Ian > >-- >Ian Camm | JANET: camm@uk.ac.man.ee.els >Dept. of Electrical Engineering | ARPA: camm@els.ee.man.ac.uk >University of Manchester, England | UUCP: ...!!ukc!man.ee.els!camm >Disclaimer: If you think I need one make it up yourself. Hope that helps anyone out there! -Mike .sig? I can't afford one .... ------------------------------------------------------------------------