kiki@uhunix1.uhcc.Hawaii.Edu (04/12/91)
The following information is from the international edition of BYTE magazine's March '91 issue. Back issues are available by calling BYTE at (603) 924-9281. The international edition adds about 150 pages to the U.S. version of BYTE and contains many ads and product announcements of firms participating at the CeBIT Hannover Fair. Two articles by Dick Pountain, Byte's contributing editor in London, concern the PgC 7600 RISC and the Taos multiprocessing OS. The PgC 7600 is touted as a second-generation RISC processor capable of 160 MIPS, Intel 80x86 emulation and embedded control. The chip will reportedly sell, in quantity, for $20. The Taos OS may also be of interest to this newsgroup, not only because of its ability to run identical code on different processers, but also because it in- fluenced design changes in the PgC 7600 processor. One of the architects of the Taos OS, Chris Hinley, is also experienced in writing games for the Atari ST and Amiga (Verminator and Onslaught). His technique of using object-oriented assembly language with a large number of macro libraries in game design was used in the construction of Taos. A fellow programmer, Nick Spicer, is using his knowledge of transputers to implement parallel processing capabilities. For further information, refer to the article starting on page 90IS-117 of the international edition of the March '91 BYTE. The following article on the Pgc 7600 is actually about three pages long. -------------------------[excerpt of PgC 7600 article]------------------------- [ The PgC 7600 RISC processor is the result of a collaboration between Chris Shelton and Sir Clive Sinclair, two computer designers. Shelton is known in the U.K. as the designer of the Nascom and SigNet computers. The Nascom was a single-board computer, while the SigNet allowed multiple users to connect with a network of close-coupled Z80 processors. Sinclair is known worldwide for his inexpensive, yet capable microcomputers, as well as many other inven- tions. Sinclair and Shelton's goal is to produce an ultra-low cost workstation by basing it on a chip that integrated computational, memory and video RAM con- trol, networking, and timer logic. ] The processor, code-named PgC7600, has been in development since 1988 by a small team led by Shelton and financed mainly by Sinclair. Computer simu- lations of the chip were completed by July 1989 and masks for making it by March '90. First samples failed because of a process fault, and second samples revealed a flaw in the RAM interface. I had timed this article to coincide with the delivery of third (working) samples of the chip, but these have been delayed. Hopefully, a PgC7600 will be running by the time this article is published. The key idea behind its design is that speeding up a RISC processor eventually takes you to a point at which you cannot keep up with getting signals on and off the chip. Shelton therefore decided to isolate the RISC CPU by completely surrounding it with on-chip peripheral-control units that handle all the comm- unications with the outside world (e.g., memory accesses, interrupts and I/O channels). The PgC contains on-chip timers video RAM support, interrupt vector generation, DMA, an I2C bus for LANS, and a memory controller (MCU) which can refresh dynamic memories. All the PgC's interfaces to the outside world have been optimized for speed. For example, the chip uses unbuffered static-column mode for RAM accesses and a small but ingenious on-chip cache (called the Q-cache) to keep the processor fed with instructions. In addition, to further improve the memory bandwidth for instruction fetches, the PgC has a simple RISC core processor with about 100 instructions, almost all of which are 1 byte long. To achieve the performance (in excess of 160 MIPS) that he believes is required to emulate other commercial CPUs in software, Shelton is implementing the PgC 7600 in a bipolar process. Because of its high power consumption, however, bipolar technology has been completely supplanted by MOS technologies. It does have its advantages: it is faster than MOS and scales down better to submicron sizes. Also, because it is current-switching rather than voltage- switching, it can drive low-impedance loads like CPU pins faster than MOS can, bringing benefits in better CPU-memory bandwidth. PgC skirts the power con- sumption problem by reducing a logic transition to 0.25 volt instead of the standard TTL 5 volt, which reduces the energy dissipation by a factor of 400. The process that PgC uses is one originally developed by Ferranti (now Plessey- GEC), called the Collector Depletor Isolation (CDI). It offers access times of 2.5 ns at the modest 1.2 micron scale. The PgC7600 will be implemented initially as a gate array that occupies a 10 by 10 mm silicon chip, but this could be reduced to 7 by 7 mm with a custom layout. Some 33% of the chip area is RAM and ROM. In CMOS, Shelton believes that the 6000 gate chip could be implemented on a 2 by 2 mm die, but performance would fall to 60 or 70 MIPS. The bipolar process requires fewer masks than does CMOS, so PgC hopes this will help them produce the chip for $20 in quantity. This, in conjunction with the fact that it requires few glue-logic chips, could make it attractive as an em- bedded controller as well as an almost glue-less CPU for low-cost workstations. The prototype PgC7600 has an integer CPU that is expected to operate at about 160 MIPS. There is no on-chip FPU. The CPU is provided with 40 registers, divided into five banks of eight. All are 32 bits wide and can be accessed in 2.5 ns, giving a processor cycle time of about 5 ns. The register architecture is designed to be scalable in future versions while maintaining compatibility with earlier versions. To achieve this, the register banks are named 0, 1, 2, 3, and TOP. When an interrupt is serviced, state information such as the accumulator and pc contents are saved only in the TOP register bank. Designers could add more banks (numbered as 0, 1, 2, 3, 4, 5 and TOP) without causing programs written for earlier versions to break. The Q-cache is a fast (2.5 ns) on-chip RAM that is 32 bytes long and can, therefore, hold an average of 32 instructions. In hardware terms, the Q-cache is implemented as a circular buffer. During sequential program execution, it gets reloaded in single-word (32-bit) chunks, thereby acting as a 32-byte moving window into main memory. When a branch instruction causes the cache to become invalid, it gets reloaded in 64-bit chunks, and each chunk can start executing while the next one is loading. Like the register architecture, the Q-cache is transparently scalable for future chip versions. The MCU is described in PgC's documentation as aggressive, and this is no exag- geration. It controls most of the PgC7600's 84 external pins, and it features separate address and data buses. The MCU uses every possible technique to optimize access to ordinary DRAM, and it supports the static-column and fast- page modes of modern DRAM chips as well as SRAM. These modes (also supported by the Acorn ARM and Intel i860) typically allow 512 consecutive data words to be accessed from the same row of a RAM chip. For inexpensive 100 ns access- time DRAM chips, the row-address select cycle time may be as much as 180 ns, but the column-access select cycle is only 55 ns, becoming the effective cycle time. The PgC generates its CAS/RAS multiplexer signals on-chip, so they add only 3 ns to the cycle time. The use of a bipolar drive for the pins allows the MCU to access memory without buffering, saving even more time. The MCU is the only part of the PgC7600 that depends on external timing. With a 16 Mhz clock, it should achieve a 25 ns cycle time with 15 ns SRAM and a 50 ns cycle time with 80 ns DRAM, providing a bandwidth between 160 and 80 mega- bytes per second. Although the original requirements for the PgC7600 to act as a full graphics processor was abandoned, the final design can still act as an integrated CRT controller. A dedicated interrupt causes a jump into a ROM subroutine, which grabs a video address from the TOP register bank, puts it into the MCU, and then requests a VRAM access cycle. Control then returns to external code, which computes the next video address. If you put your video-synchronous sig- nal onto this interrupt pin, the PgC7600 becomes a CRT controller for video buffers implemented with VRAM chips. Shelton estimates that controlling a 1024 by 768 pixel by 8-bit video buffer in this way would consume about 1 per- cent of CPU time. The original purpose of the high performance promised by the PgC7600 was for full-speed emulation of other processors, especially the Intel 8086 family, in software, allowing the chip to drive a low-cost IBM PC-compatible work- station. However, PgC is now envisaging broader applications. Though the chip does not have special communication hardware like that of the Inmos transputer, its fast memory access would enable it to be used in parallel- processing systems where shared memory is the communication channel between processors. This sort of system would be ideal for running distributed message-passing operating systems such as Helios or Taos (see my article: "Taos: An Innovation in Operating Systems"). PgC has been in close contact with the developers of both operating systems and has even modified the instruction set of the PgC to better accommodate the Taos's message-passing scheme. As mentioned, the Pgc7600 has no hardware for floating-point arithmetic, which would seem to disqualify it from supercomputer applications. However, Shelton argues with some conviction that the superior processor-to-memory bandwidth can be exploited here. The Pgc7600 could feed floating-point data into pseudo- registers held in dual-ported RAM. From there, the data would be autonomously transferred into a streamed FPU, such as those from AMD, Weitek, or Cyrix, and the answers would be transferred back by the same means. Using 15 ns SRAM pseudo-registers, the PgC7600 should be capable of transferring data at 160 MBps (1280 Mbps). If each floating-point operation involved 100 bits, a three- operand scheme could sustain the quoted peak rate of the FPU, which could be up to 33 million single-precision floating-point operations per second. Combining this with the parallel scheme would allow pipelines of many PgC7600s to be con- structed to deliver supercomputer performance. Another intriguing possibility, given Sinclair's Anamartic connections, would be wafer-scale integration, for which the 6000 gate PgC design is an ideal can- didate. We'll see what happens. ----------------------------[end of excerpt]----------------------------------- For $20, this thing sounds potent, especially in combination with the Taos OS. The article alludes to the other ventures of Sir Clive Sinclair and I recall that he was supposed to be developing a silicon "hard drive", so that it is very possible that our conceptions of power and price may be radically altered. Though I don't question Sinclair's and Shelton's genius, I have some doubts about Sir Clive's business acumen. The Timex, Quantum QL, Cambridge Computer, and Psion are all pretty good machines, but they had some quirks and were not supported by further development. I think Atari might be in a better position to deliver and support a marketable product based on the PgC chips, because of their experience with the Inmos transputer and Helios OS, which culminated in the ATW computer. For the complete article, contact BYTE Back Issues, One Phoenix Mill Lane, Peterborough, NH 03458, (602) 924-9281. In Europe, send requests to BYTE Back Issues, c/o Dynamic Graphics International, P.O. Box 25, 3950 AA Maarn, The Netherlands. Jack
plinio@turing.seas.ucla.edu (Plinio Barbeito) (04/13/91)
In article <12430@uhccux.uhcc.Hawaii.Edu> kiki@uhunix1.uhcc.Hawaii.Edu writes: > >The following information is from the international edition of BYTE magazine's >March '91 issue. Back issues are available by calling BYTE at (603) 924-9281. > [...some parts of excerpt deleted...] > >It does have its advantages: it is faster than MOS and scales down better to >submicron sizes. Also, because it is current-switching rather than voltage- >switching, it can drive low-impedance loads like CPU pins faster than MOS can, >bringing benefits in better CPU-memory bandwidth. PgC skirts the power con- >sumption problem by reducing a logic transition to 0.25 volt instead of the >standard TTL 5 volt, which reduces the energy dissipation by a factor of 400. Sounds good, but does this mean that standard RAM chips will be incompatible with the bipolar version of the PgC? I hope this is not true of the other version, at least. >----------------------------[end of excerpt]----------------------------------- > >For $20, this thing sounds potent, especially in combination with the Taos OS. Pretty amazing stuff. This thing uses tricks to get seemingly impossible cycle times from normal RAM chips. The possibility that an inexpensive system could be built from this fast part is then far more likely. Seeing the details also lends the product a bit more credence. >I think Atari might be in a better position to deliver and support a marketable >product based on the PgC chips, because of their experience with the Inmos >transputer and Helios OS, which culminated in the ATW computer. I'm confident of Atari's ability to create excellent hardware, and even software, but seeking them out for the strength of their marketing of the ATW sounds funny somewhere :-). As far as predicting what they will do, sometimes it's easier to disbelieve their representatives about this than to believe them. For example, if Leonard says that Atari will never use the '040, what would this imply to you: 1) that they will use SPARC, MIPS or PgC, etc. in their next machine and port TOS/GEM to it. 2) they are simply going to discontinue the ST/TT line. 3) they are going to use the 040 anyway but don't want to tell you now so you won't put off buying a TT. Thanks for posting an interesting article that a lot of us would not ordinarily have access to. We may never see an Atari product out of this, but at least you have helped to establish the PgC as a credible option ($20 for 160MIPS still sounds a bit off the far end, though). plin -- ----- ---- --- -- ------ ---- --- -- - - - plinio@seas.ucla.edu Is this the TV news? I thought I was watching a soap opera!
zuschlag@diku.dk (Jesper Zuschlag Madsen) (04/17/91)
kiki@uhunix1.uhcc.Hawaii.Edu writes: >For $20, this thing sounds potent, especially in combination with the Taos OS. >The article alludes to the other ventures of Sir Clive Sinclair and I recall >that he was supposed to be developing a silicon "hard drive", so that it is >very possible that our conceptions of power and price may be radically altered. >Though I don't question Sinclair's and Shelton's genius, I have some doubts >about Sir Clive's business acumen. The Timex, Quantum QL, Cambridge Computer, >and Psion are all pretty good machines, but they had some quirks and were not >supported by further development. I just have to correct you at this subject! The Timex computers where special versions of the sinclair ZX 81 and ZX Spectrum. Perhaps they didn't sell very well in USA, but were some of the best selling micro(home) computers ever in europa (the spectrum and its succesor the Sam Coupe, are still selling quite well). The sinclair QL (the name is NOT Quantum QL) where fare ahead from all other compters in it's days. Ok it was not as great succes! but there is still about 100.000 users around the world. Neither Clive Sinclair or Chris Shelton has anything to do with the Psion computers (organiser I and II, MC200/400/600). All very fine computers, but overpriced. On the other hand is the Cambridge Computer Z88 one of the best selling notebook computer ever, and is still going strong (rumors says that we soon will see a new version, perhaps the Z91?). >I think Atari might be in a better position to deliver and support a marketable >product based on the PgC chips, because of their experience with the Inmos >transputer and Helios OS, which culminated in the ATW computer. I totaly disagree! With a PgC7xxx in their hands, Atari would just make some kind of ST compatible (with TOS and GEM- don't joke me!). If anyone are going to make something radical new, then it has to be men like Sinclair and Shelton. Personally I'm looking forward to see what they will come out with (around fall/winter 1991 perhaps?) >For the complete article, contact BYTE Back Issues, One Phoenix Mill Lane, >Peterborough, NH 03458, (602) 924-9281. In Europe, send requests to BYTE >Back Issues, c/o Dynamic Graphics International, P.O. Box 25, 3950 AA Maarn, >The Netherlands. >Jack - Jesper Zuschlag (zuschlag@freja.diku.dk) Department of Computer Science, University of Copenhagen.