meulenbr@cst.prl.philips.nl (Frans Meulenbroeks) (06/11/91)
Hi, I've been told that the Mega STe can switch the processor speed. Most likely this is controlled to write some magic value into some unknown register. Unfortunately the local Atari Subsidiary could not supply me with that info, since they could not get it from Atari Sunnyvale. Is there someone on the net who perhaps knows this information? Or could someone with a Mega STe (I don't have one) look into this and disassemble the bios call which does the speed switching, and post the results of this disassembly (or mail me the disassembled code so I can dig in it myself). Thanks! -- Frans Meulenbroeks (meulenbr@prl.philips.nl) Centre for Software Technology
larserio@IFI.UIO.NO (LarsErikOsterud) (06/12/91)
Here are routines for switching both MEGA STE and HYPERCAHE
between 16 Mhz with cache and 8 Mhz without cache....
The subroutines cache_on and cache_off must be called from
inside supervisor mode as they access restricted adresses.
cache_on: cmpi.b #2,$2.w ;TOS 2.xx (MEGA STE) ?
bne.s hyper_on ;No, Hypercache on
bset.b #1,$FFFF8E21.w ;Yes, 16 Mhz speed
bset.b #0,$FFFF8E21.w ;Switch cache on
rts
cache_off: cmpi.b #2,$2.w ;TOS 2.xx (MEGA STE) ?
bne.s hyper_off ;No, Hypercache off
bclr.b #0,$FFFF8E21.w ;Yes, Cache off
bclr.b #1,$FFFF8E21.w ;Switch to 8 MHz
rts
hyper_on: move.l #$1E0040,-(sp) ;GPO signal on = Hypercache on
bra.s set_cache
hyper_off: move.l #$1DFFBF,-(sp) ;GPO signal off = Hypercache off
set_cache: trap #14 ;Xbios
addq.l #4,sp
rts
Lars-Erik / ABK-BBS +47 2132659 / ____ ______ ________________________
Osterud / larserio@ifi.uio.no / /___ / The norwegian ST
__________/ ______________________/ ____/ / Klubben, user associationstephen@oahu.cs.ucla.edu (Steve Whitney) (06/12/91)
In article <CMM.0.90.2.676685451.larserio@kvart.ifi.uio.no> larserio@ifi.uio.no writes: >Here are routines for switching both MEGA STE and HYPERCAHE >between 16 Mhz with cache and 8 Mhz without cache.... ... >cache_on: cmpi.b #2,$2.w ;TOS 2.xx (MEGA STE) ? I don't think that Atari has guaranteed that only MegaSTEs will have TOS 2.xx. A safer way to determine this would be to check the cookie jar. You can just do it once and store the value somewhere. --Steve > > Lars-Erik / ABK-BBS +47 2132659 / ____ ______ ________________________ > Osterud / larserio@ifi.uio.no / /___ / The norwegian ST >__________/ ______________________/ ____/ / Klubben, user association -- Steve Whitney - UCLA CS Grad Student (())_-_(()) Soon to be working at Silicon Graphics | (* *) | Internet: stephen@cs.ucla.edu UCLA Bruin--> { \_@_/ } GEnie: S.WHITNEY `-----'
danny@fiction.ms.sub.org (Daniel Roedding) (06/16/91)
meulenbr@cst.prl.philips.nl (Frans Meulenbroeks) writes: > I've been told that the Mega STe can switch the processor speed. > Most likely this is controlled to write some magic value into some > unknown register. Speed and cache status are controlled by the lowest two bits of the byte 0xffff8e21. Daniel