[comp.sys.amiga] Atari Transputers ? & A British ST/Amiga Rival ? Really MIPS

tim@amdcad.AMD.COM (Tim Olson) (01/01/70)

In article <1477@pdn.UUCP> alan@pdn.UUCP (0000-Alan Lovejoy) writes:
+-----
| In article <18505@amdcad.AMD.COM> tim@amdcad.UUCP (Tim Olson) writes:
| /and on many RISC machines it requires only 1:
| /
| /	add	a, b, c
| /
| 
| That last example is a good example of a VAX-class CISC machine, not
| of any RISC machine I know of.  
+-----

MIPS, SPARC, H-P Spectrum, and the Am29000 are all three-address
(register-to-register) architectures... 

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)

tim@amdcad.AMD.COM (Tim Olson) (10/02/87)

Summary:


In article <1138@water.waterloo.edu> ljdickey@water.waterloo.edu (Lee Dickey) writes:
| In article <607@sbcs.UUCP> root@sbcs.UUCP (Root) writes:
| >> >      One article I have seen quotes the performance of the slower T414
| >> >      processor (20 mhz) as 10 MIPS !
| >
| >	RISC mips, unfortunately. 
| 
| You seem to imply that RISC mips are not quite as good as some other kind
| of MIPS.  Are RISC mips slower somehow?  Are more instructions needed to
| produce the same results?   Explain, please.

Actually, the term should be "Native MIPS" (Millions of machine
Instructions per Second), as opposed to "Vax MIPS" (How fast is this
machine as compared to a VAX 11/780).  A MIPS number depends greatly upon
processor architecture and benchmarks chosen.

For example, the transputer is a stack machine.  To perform the sequence

	a = b+c;

(assuming a,b, and c are register variables) requires 4 instructions:

	push b
	push c
	add
	pop a

while on the 68000 it requires 2:

	mov b, a
	add c, a

and on many RISC machines it requires only 1:

	add	a, b, c

However, it is generally true that RISC machines require more
instructions to perform an operation than CISC machines (a trade-off for
faster instructions).  For example, the Am29000 runs at around 17
(Native) MIPS sustained, which roughly corresponds to 13 VAX MIPS. 
The correspondance varies with the benchmark -- on different programs,
the same 17 Native MIPS has varied from 10 to 27 VAX MIPS!

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)

alan@pdn.UUCP (Alan Lovejoy) (10/04/87)

In article <18505@amdcad.AMD.COM> tim@amdcad.UUCP (Tim Olson) writes:
/For example, the transputer is a stack machine.  To perform the sequence
/
/	a = b+c;
/
/(assuming a,b, and c are register variables) requires 4 instructions:
/
/	push b
/	push c
/	add
/	pop a
/
/while on the 68000 it requires 2:
/
/	mov b, a
/	add c, a
/
/and on many RISC machines it requires only 1:
/
/	add	a, b, c
/

That last example is a good example of a VAX-class CISC machine, not
of any RISC machine I know of.  RISC code would probably be identical
to the 68000 example (which is more of a RISC machine than it is given
credit for--just wait until the 78000 is announced and you'll see what
I mean).

Also, assuming that the values (a, b, c) are already in registers
obscures the difference between RISC and 68000.  Assuming memory values
gives:

   RISC              680x0               VAX

   LOAD a(FP), R0    MOVE.W a(A6), D0    ADD a(R1), b(R1), c(R1)
   LOAD b(FP), R1    ADD.W b(A6), D0 
   ADD R0, R1        MOVE.W D0, c(A6)
   STORE R1, c(FP)
  
The RISC code will run in 4 cycles; on a 68030 with no-wait-state memory
the 680x0 code will take at least 3 cycles but could take as many as 10 cycles 
and will probably average 5 or 6 cycles, although that will depend on the 
state of the instruction pipeline and on what's currently in the code and data 
caches; I don't have enough information about the VAX instruction set to give 
cycles--it probably is different for each VAX model anyway.

--alan@pdn