djn@nmtsun.nmt.edu (Northrop) (06/08/88)
In article <573@osupyr.mast.ohio-state.edu> vkr@osupyr.mast.ohio-state.edu (Vidhyanath K. Rao) writes: >(Changing the subject quickly he said) as indeed I did >I heard about a RISC chip that is (source? machine?) code compatible with >the 68000. [No that is not the 88000]. What is the low down on that? If it's code compatible with the 68000 then it would have to implement the 68000 instruction set, no? So, that's not very reduced is it? Yours in pedantificationalismosis, -- djn djn@nmtsun.nmt.edu ...!unmvax!nmtsun!djn --- Message Ends ---
gore@eecs.nwu.edu (Jacob Gore) (06/10/88)
/ comp.sys.amiga / daveh@cbmvax.UUCP (Dave Haynie) / Jun 8, 1988 / >There is a RISCy CPU set ... it claims to be fully object code compatible >with the 68000. Me confused... How can you have a RISC CPU that is object-compatible with a CISC CPU? Jacob Gore Gore@EECS.NWU.Edu Northwestern Univ., EECS Dept. {oddjob,gargoyle,ihnp4}!nucsrl!gore
dca@kesmai.COM (David C. Albrecht) (06/10/88)
> >I heard about a RISC chip that is (source? machine?) code compatible with > >the 68000. [No that is not the 88000]. What is the low down on that? > If it's code compatible with the 68000 then it would have to > implement the 68000 instruction set, no? So, that's not very reduced is it? Well when you get right down to it most so called 'RISC' processors aren't really RISC either. I haven't heard of any 'chips' that are 68000 compatible. I have heard of a company (I think it was called Edge) which re-implemented the 68000 instruction set in high speed CMOS gate arrays. They produced the RISC-like concept of every instruction executing in one cycle. The sucker really flys but I don't remember the exact numbers (I thought it was in the 10Mips+ range). This is not a low cost solution however, but rather an expensive substitute for high-line machines which need to exceed the performance of the 68020/30. David Albrecht
daveh@cbmvax.UUCP (Dave Haynie) (06/14/88)
in article <10260013@eecs.nwu.edu>, gore@eecs.nwu.edu (Jacob Gore) says: >>There is a RISCy CPU set ... it claims to be fully object code compatible >>with the 68000. > Me confused... How can you have a RISC CPU that is object-compatible > with a CISC CPU? Hmmmm. Must tell you something about the quality of 68000 instructions, eh? And, of course, the definition of RISC, which really isn't. > Jacob Gore Gore@EECS.NWU.Edu > Northwestern Univ., EECS Dept. {oddjob,gargoyle,ihnp4}!nucsrl!gore -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {ihnp4|uunet|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy "I can't relax, 'cause I'm a Boinger!"
mph@rover.UUCP (Mark Huth) (06/16/88)
In article <10260013@eecs.nwu.edu> gore@eecs.nwu.edu (Jacob Gore) writes: >/ comp.sys.amiga / daveh@cbmvax.UUCP (Dave Haynie) / Jun 8, 1988 / > >>There is a RISCy CPU set ... it claims to be fully object code compatible >>with the 68000. > >Me confused... How can you have a RISC CPU that is object-compatible >with a CISC CPU? Well, the Edge machine is not a RISC machine. It is a proprietary gate-array implementation of the 68000 that runs with a faster clock. RISC machines could be made object compatible with various CISC processors by compiling the CISC object code into the RISC instruction set. The object wouldn't actually run, but a derivatiive of the object could be produced. Mark Huth
daveh@cbmvax.UUCP (Dave Haynie) (06/17/88)
in article <780@rover.UUCP>, mph@rover.UUCP (Mark Huth) says: > In article <10260013@eecs.nwu.edu> gore@eecs.nwu.edu (Jacob Gore) writes: >>/ comp.sys.amiga / daveh@cbmvax.UUCP (Dave Haynie) / Jun 8, 1988 / >>>There is a RISCy CPU set ... it claims to be fully object code compatible >>>with the 68000. >>Me confused... How can you have a RISC CPU that is object-compatible >>with a CISC CPU? > Well, the Edge machine is not a RISC machine. It is a proprietary > gate-array implementation of the 68000 that runs with a faster clock. Well I said RISCy. That's because there is no absolute definition of RISC. RISC is to CPU architecture as Artifical Intelligence is to Software architecture. No one builds a pure RISC CPU, no one builds a pure AI program, outside of perhaps pure theory. And that's because both RISC and AI are a collection of basic concepts, no a single thing that can be easily defined. I might use some RISC concepts like pipelining, load/store instruction set, massive register set, Harvard dual bus, scoreboarding, ~1 cycle/instruction, etc. in a CPU. Many of these concepts existed before anyone ever said RISC. Put a few of 'em together in 1988 and someone calls it RISC. Similarly, I might use hill climbing, AND/OR trees, heuristics, production systems, logical inferencing, etc. in a program. Many of these concepts existed before anyone ever said AI, but put these together in a program in 1988 and folks will say you're using AI. As far as the Edge machine goes, it's got a lot of RISC ideas in it's architecture, which is why I called RISCy. It claims 1.4 cycles per instruction on an average, which is much closer to the 88000 than any of the 680x0 family today. It uses a Harvard architecture, with five separate buses. The 88000 uses a Harvard architecture, with two external buses and 3 internal buses. It uses two deep pipelines, much like the 88000. It can even run in a multiprocessor setup, like the 88000. The Edge 1200 claims 11 sustained MIPs, the 20MHz 88000 claims 12. In the final analysis, though, the Edge machine looses. It fills a whole board, and systems start at $50,000. The 88000 is a three chip set, and a system could probably be designed for $10,000. They both run UNIX. In fact, I always wondered by Edge bothered with 68010 compatibity. It's an interesting design study, and a good indication of what Motorola's likely to be able to achieve with the 68040 and maybe beyond. But you don't need a compatible architecture to run UNIX. I need one, 'cause I want to run AmigaOS. But I'll pay $50 for the CPU, or maybe even $100. No more, please. > Mark Huth -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {ihnp4|uunet|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy "I can't relax, 'cause I'm a Boinger!"
vkr@osupyr.mast.ohio-state.edu (Vidhyanath K. Rao) (06/18/88)
Here are some of my silly musings on how to design a RISCy 68000 SOURCE compatible chip i.e the assembler will eat 68000 assembly source, but will NOT map it 1-1. In particular the multiply/divide will be replaced by loops. (So your multiplication will interrepted by interrupts but should you care?) Here it comes: We have to live with the bit-twiddling and the plethora of addressing modes on all the basic instructions. But we will try to get as much parallelism as possible. The aim is to be like 6502: The extra memory references must cost only one cycle each. In any case 68000 doesn't do double indirection from memory so we don't have the throw-away cycles. Of course the branches and jumps still cost too much. This leaves the interrupt service. I don't think that this can be changed. So this is another pain we have to put up with. The icing on the cake will be a big register cache so that subroutines etc can just switch register windows. There is a hidden cost: The instructions will be 1, 2, or 3 longwords long. But we will NOT have 2^32 instruction/addressing mode combinations. There may several different NOPs for example. Memory is cheap (he says). Being somebody who couldn't build a slidepot based controller I don't presume to say that this could be done. But would like it picked to pieces. I have just donned my asbestos shields :-)