sword@vu-vlsi.Villanova.EDU (David Talmage) (07/07/88)
In _Amazing Computing_ Volume 3, Number 3, Perry Kivolowitz tells us how to improve the grounding of four PALS on the daughter board of our A1000's. This change may make the A1000 less prone to mysteriously crashing. My problem: the text and the illustration don't agree. The text says to connect the top left pins of PALs J&K and L&N. The picture shows J&K connected per the text but L&N aren't connected by their top left pins. Instead, the picture shows L&*K* connected by their top *right* pins. If someone who has done this modification successfully could clarify the article, I'd be one happy camper. Thanks! David Talmage UUCP: sword@vu-vlsi, talmage@excalibur BITNET: talmage@vuvaxcom ARPA: talmage%vuvaxcom.bitnet@a-gateway-near-you
rusty@hocpa.UUCP (M.W.HADDOCK) (07/07/88)
In article <1666@vu-vlsi.Villanova.EDU> sword@vu-vlsi.Villanova.EDU (David Talmage) writes: >In _Amazing Computing_ Volume 3, Number 3, Perry Kivolowitz tells us how >to improve the grounding of four PALS on the daughter board of our A1000's. >This change may make the A1000 less prone to mysteriously crashing. > >My problem: the text and the illustration don't agree. The text says to >connect the top left pins of PALs J&K and L&N. The picture shows J&K >connected per the text but L&N aren't connected by their top left pins. >Instead, the picture shows L&*K* connected by their top *right* pins. > Believe the text. To quote said magazine, on page 102, (diagram without permission) J K L N *********** *********** * * * * o+----+o o+----+o o+----+o o+----+o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| |o o| () |o o| () |o o| () |o o| () |o <--- these are chip notches o+----+o o+----+o o+----+o o+----+o * * * * *********** *********** |<- .6" ->| Figure Two: Front of A1000 "The diagram on page 59 of the "PAL Help" article in AC V3.3 was incorrect. The correct diagram is presented above. The article text was correct and following those directions would have made the error obvious. We apologize for any inconvience caused by our error." -- Rusty Haddock {uunet!likewise,cbosgd,rutgers!mtune}!hocpa!rusty AT&T Consumer Products Laboratories - Human Factors Laboratory Holmdel, New Joyzey 07733 (201) 834-1023 rusty@hocpa.att.com
eric@hector.UUCP (Eric Lavitsky) (07/07/88)
In article <1666@vu-vlsi.Villanova.EDU> sword@vu-vlsi.Villanova.EDU (David Talmage) writes: >My problem: the text and the illustration don't agree. The text says to >connect the top left pins of PALs J&K and L&N. The picture shows J&K >connected per the text but L&N aren't connected by their top left pins. >Instead, the picture shows L&*K* connected by their top *right* pins. A correction was published in the following issue, I believe. In any event, follow the text - the illustration is wrong (it was changed by some layout guy). Cheers, Eric Lavitsky, ASDG Incorporated ARPA: eric@topaz.rutgers.edu or eric@ulysses.att.com UUCP: {wherever!}ulysses!eric or {wherever!}rutgers!topaz!eric SNAIL: 34 Maplehurst Ln, Piscataway, NJ 08854 "To err is human; To really f*ck up requires the root password."
charles@hpcvca.HP.COM (Charles Brown) (07/08/88)
>My problem: the text and the illustration don't agree. The text says to >connect the top left pins of PALs J&K and L&N. The picture shows J&K >connected per the text but L&N aren't connected by their top left pins. >Instead, the picture shows L&*K* connected by their top *right* pins. > David Talmage I have made the mod. The text is correct. The picture is off by one line. You can verify for yourself what should be connected with an Ohmmeter. You will only be connecting lines which already show 0ohms between them. You are fixing high frequency problems, not DC. Charles Brown
Doug_B_Erdely@cup.portal.com (07/08/88)
David,
I have a 30 Meg Supra drive that would get random read write errors..
I talked to someone here on the net who was VERY nice about helping me out
with the problem of HOW to ground the PAL Chips. <Hi John KJellman>!
I did as he had done... but I was STILL having trouble... I called Supra
and they told me a COMPLETLY different method to use... AND IT WORKED!!!!
This is what they told me....
1. Connect pin 10 (upper left pin when your looking at the daughter board
while it is STILL in the Amiga> of all 4 PAL chips together...
2. then from your four chips with their pin 10's all connected together, go
to the Electrolytic<SP?> capacitor <GROUND SIDE!> about an inch or so away
from the PAL's....
3. From the Capacitor, go down to the mother board and connect to ground!
I found a nice ground pad right by the power connector from the power supply,
and soldered the wire right to the pad... Since I did this about 2 days ago
I have not had ONE read/write error or ANY bit of strangeness from the
hard drive. Including being told that a known program is not an object
module... All of this has gone away since I did the above mentioned
modification!
- Doug -
Doug_B_Erdely@Portal.Cup.Comsword@vu-vlsi.Villanova.EDU (David Talmage) (07/11/88)
In <1666@vu-vlsi.Villanova.EDU> I ask for someone to clarify a mismatch between the text and the illustration of an A1000 PAL grounding project described by Perry Kivolowitz in AC V3.3. Several people were gracious enough to reply. They are: rusty@hocpa.UUCP (M.W.HADDOCK), who posted a corrected illustration from AC V3.4 in article <343@hocpa.UUCP>; charles@hpcvca.HP.COM (Charles Brown) who, in <5660001@hpcvca.HP.COM>, tells us how to use an ohm meter to find the right lines to connect; Doug_B_Erdely@cup.portal.com, who tells us of yet another way to ground our PALS in article <7201@cup.portal.com>. His fix comes from the SUPRA people. Also, kjohn@richp1.UUCP (John Kjellman) sent e-mail explaining the correction. Shortly after I posted my query, I temporarily lost Net access. About that time, I stumbled on the phone number of ASDG and called them. Mr. Kivolowitz, who was gracious enough to speak to me directly, said that the text was indeed correct but the illustration was not. My thanks to everyone who took the time to help me out. I'm going to apply the fix tomorrow. I'm doubly excited about it 'cause if it works then I'll be able to use both my 2MB ASDG board and my new C-LTD SCSI controller at the same time. Oh Boy! David UUCP: sword@vu-vlsi, talmage@excalibur BITNET: talmage@vuvaxcom ARPA: talmage%vuvaxcom.bitnet@a-gateway-near-you
king@client2.DRETOR.UUCP (Stephen King) (07/12/88)
In article <1666@vu-vlsi.Villanova.EDU> sword@vu-vlsi.Villanova.EDU (David Talmage) writes: >In _Amazing Computing_ Volume 3, Number 3, Perry Kivolowitz tells us how >to improve the grounding of four PALS on the daughter board of our A1000's. >This change may make the A1000 less prone to mysteriously crashing. I found this mod necessary when using a 2Meg board & Comspec SCSI adaptor slapped onto my 1000 here at work. >My problem: the text and the illustration don't agree. The text says to >connect the top left pins of PALs J&K and L&N. The picture shows J&K >connected per the text but L&N aren't connected by their top left pins. >Instead, the picture shows L&*K* connected by their top *right* pins. I don't have the illustration to look at, but here is what I did: Connect: J10-K10-L10-N10-P11-Q11-MotherBoardGround It seems that J,K,L & N should all have the same pins grounded, but P & Q use the pins on the other side of the package. This is because some chips are viewed from the bottom and others from the top. When in doubt, check the data sheet for the chip. Most (normal) chips have ground in the bottom left corner of the package, when viewed from the top with the little notch upwards (pin 1 in upper left corner). +5V supply is the top right pin, diagonally opposed to ground. Note that dynamic RAM chips are (always ?) backwards, presumeably because they were invented by IBM :-) * These are the facts as I understand them, my employer may or may not agree, depending on the prevailing wind and other important factors. --- Stephen J King - Simulation & Training, DCIEM - ...{utzoo|mnetor}!dciem!dretor!king (at least, for the time being)