ntm1477@dsacg3.UUCP (Jared McNeal) (08/27/88)
1. Why did commodore drop the transputer ? 2. What types of O/S can run with the transputer ? 3. Where can i find some info on this subject ? 4. What is the difference between a parallel processor and the transputer. Thank you Jared A McNeal
root@sbcs.sunysb.edu (root) (08/27/88)
In article <989@dsacg3.UUCP>, ntm1477@dsacg3.UUCP (Jared McNeal) writes: > 1. Why did commodore drop the transputer ? If this is the case, it must have been done by some clear thinking individuals in the engineering department. One wonders what the transputer might have become if fielded five years ago. Today (with 20 MIP RISC processors) it just isn't worth a second glance. > 2. What types of O/S can run with the transputer ? > 3. Where can i find some info on this subject ? > 4. What is the difference between a parallel processor and the transputer. > > Thank you > Jared A McNeal Rick Spanbauer SUNY/Stony Brook
vkr@osupyr.mast.ohio-state.edu (Vidhyanath K. Rao) (08/29/88)
In article <1544@sbcs.sunysb.edu>, root@sbcs.sunysb.edu (root) writes: > One wonders what > the transputer might have become if fielded five years ago. Today > (with 20 MIP RISC processors) it just isn't worth a second glance. I thought that the point of the transputer was 'painless' parallel processing. Do RISC chips include this as a matter of course? Of course hypercube and such are for a limited market. Perhaps what one may want is to use the Amiga as a front end to such beasts (?). -Nath vkr@osupyr.mast.ohio-state.edu
mlelstv@faui44.informatik.uni-erlangen.de (Michael van Elst ) (08/29/88)
In article <989@dsacg3.UUCP> ntm1477@dsacg3.UUCP (Jared McNeal) writes: >1. Why did commodore drop the transputer ? >2. What types of O/S can run with the transputer ? >3. Where can i find some info on this subject ? >4. What is the difference between a parallel processor and the transputer. Hello, I try to answer briefly: 1. - noone knows, did they really drop ? I saw a transputer board working in an A2000 at the CEBIT fair. 2. - I know of a O/S called Helios that runs on several types of transputer boxes. It seems to be a well designed O/S using a tree file system that includes devices (like UNIX) and even process descriptors, memory segements and everything. Helios is developed by a british company named Perihelion. The transputer card I saw in the Ami worked with Helios. 3. call INMOS (they built the transputer). They will send you anything about the transputer chip. 4. There are some different kinds of parallel machines. The common architecture is a vector processor that uses parallel arithmetic units to work on multiple operands with a single instruction. Then you have field processors that have multiple execution units working on different parts of a program (or different programs) at the same time. To communicate between different processes you can use shared memory or message passing. Shared memory is somehow complicated with more processors as you have to arbitrate the accesses of many clients. Message passing (through separate data channels) needs methods to propagate information through the multiprocessor for you cannot connect all processors with each other. This type of architecture is a transputer. It is a small processor with a small amount of very fast memory (and more slower memory). It has four high speed data channels (called links) used for communication. INMOS has built some features into the chip to improve speed and generality like a (more or less) reduced instruction set (RISC), builtin task switch instructions and bootloading through a link. Michael van Elst
yann@ai.toronto.edu (Yann le Cun) (08/30/88)
In article <1544@sbcs.sunysb.edu>, root@sbcs.sunysb.edu (root) writes: > One wonders what > the transputer might have become if fielded five years ago. Today > (with 20 MIP RISC processors) it just isn't worth a second glance. but the transputer *IS* a *cheap* 20 MIPS RISC processor, well, make that 10 MIPS and put two of them. Yann le Cun yann@ai.toronto.edu
root@sbcs.sunysb.edu (root) (08/31/88)
In article <88Aug29.235507edt.661@neat.ai.toronto.edu>, yann@ai.toronto.edu (Yann le Cun) writes: > In article <1544@sbcs.sunysb.edu>, root@sbcs.sunysb.edu (root) writes: > > One wonders what > > the transputer might have become if fielded five years ago. Today > > (with 20 MIP RISC processors) it just isn't worth a second glance. > > but the transputer *IS* a *cheap* 20 MIPS RISC processor, well, make > that 10 MIPS and put two of them. Yeah, and for certain problems you get superlinear speedup. But on the "standard" benchmarks, ie dhrystone the transputer does perhaps 7K dhrystone when running on chip. Maybe 3K off chip. On the other hand the AMD29000 does about 20K+ dhrystones. 20K/3K=~6.7 transputers + memory cost much more than one AMD29K. > Yann le Cun yann@ai.toronto.edu Rick Spanbauer SUNY/Stony Brook
daveh@cbmvax.UUCP (Dave Haynie) (08/31/88)
in article <821@osupyr.mast.ohio-state.edu>, vkr@osupyr.mast.ohio-state.edu (Vidhyanath K. Rao) says: > I thought that the point of the transputer was 'painless' parallel > processing. Do RISC chips include this as a matter of course? Painless is a relative term. The transputer is designed for loosely coupled parallel processing by virtue of some serial links available in each chip. Transputer chips typically sport 4 links each, so each one can connect to 4 other Transputers or link based devices relatively painlessly. And the Transputer software model is designed to help facilitate this multiprocessing in that you don't really care whether several tasks are running on the same or on different machines. At least, that's the theory. There are some problems with it. It's pointless to try and build a tightly coupled multiprocessing system with Transputers. They don't support MMUs, and they're not all that fast on their own (in the range of a plain 68020). Many of the newer RISC and CISC machines will allow you to build very painless tightly-coupled multiprocessor system. A tightly coupled architecture doesn't extend to N as does a loosely coupled system, but being tightly coupled doesn't prevent you from handling loosely coupled concepts as well. A serial link that works just as well as the Transputer link could certainly be an add-on to any microprocessor system; that's to a great deal what you're going to get in a LAN anyway, and there are LANs that go faster than Transputer links. > Of course hypercube and such are for a limited market. Perhaps what one > may want is to use the Amiga as a front end to such beasts (?). That seems to be the way Transputer folks, mainly in Europe, are planning it. > -Nath > vkr@osupyr.mast.ohio-state.edu (I'm not associated with any Transputer projects at Commodore; I work on 32 bit 680x0 systems). -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {ihnp4|uunet|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy "I can't relax, 'cause I'm a Boinger!"
daveh@cbmvax.UUCP (Dave Haynie) (08/31/88)
in article <88Aug29.235507edt.661@neat.ai.toronto.edu>, yann@ai.toronto.edu (Yann le Cun) says: > >> the transputer might have become if fielded five years ago. Today >> (with 20 MIP RISC processors) it just isn't worth a second glance. > but the transputer *IS* a *cheap* 20 MIPS RISC processor, well, make > that 10 MIPS and put two of them. > Yann le Cun yann@ai.toronto.edu In any REAL Transputer environment, it comes out looking more like a 2-3 MIPS machine at best. The Transputer is RISCy, in that it uses some RISC concepts, but it also misses alot of them. It's got that nice 4k of very fast RAM on chip, but it's not cache RAM. So you pay a big penalty for going off-chip to get memory and the off-chip memory interface is real slow. And from a programming point of view the Transputer is a weird stack machine that requires lots of instructions to do things and doesn't give you real registers. Add it all up and no Transupter gives you a reasonable bang per buck. Even in multi-Transputer systems you may still be in trouble. A 68030 loosely coupled multiprocessing system would require 1/2 less than half the number of CPUs that a similar Transputer system would. I could build a killer link interface external to the '030 for the money I'd save there. And I'd get memory mapping and protection as well, which you don't get at all on the Transputer. -- Dave Haynie "The 32 Bit Guy" Commodore-Amiga "The Crew That Never Rests" {ihnp4|uunet|rutgers}!cbmvax!daveh PLINK: D-DAVE H BIX: hazy "I can't relax, 'cause I'm a Boinger!"
thomax@netmbx.UUCP (Thomas) (09/04/88)
In article <4602@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes: > >At least, that's the theory. There are some problems with it. It's pointless >to try and build a tightly coupled multiprocessing system with Transputers. >They don't support MMUs, and they're not all that fast on their own (in the >range of a plain 68020). sorry. sure, an t414 is not fast as a plain 68020, but the power of transputer is grown up proportinal to the number of links you use. yet you can see there is no entitle to compare a 680x0 with an transputer. mgh thomax -- *============================================================================* | thomax@netmbx.UUCP Thomas Kaulmann | | ...{pyramid|altger|unido}!netmbx!thomax Alexandrinenstr. 42 | | "the Killer Ducks are comming!!!" 1000Berlin61 |