451061%UOTTAWA.BITNET@cornellc.cit.cornell.edu (Valentin Pepelea) (12/12/88)
< If only the line eater lived in Berlin.... >
I need to add a 68851 MMU into the Lucas board for a 4th year University
project I am working on. The design, as described by the block diagram of
page B-2 of the MC68851 User's Manual seems quite simple, but I don't have
enough practical electronics experience to be certain about it. Here is a
description of the schematic I came up with; if you have any experience
designing 680x0 boards, please take a look at it. For each hour of your time
you will save me a dozen hours of headackes.
Please pay particular attention to the logic functions presented and any
potentially missing pull-up resistors. (How do you know where to put those?)
And did I forget to add some logic somewhere?
DESCRIPTION
The following pins on the 68851 will be connected to the 96-pin Din of the
Lucas board:
68851 to 96-pin Din
--------------------------------
LA8-LA23 A8-A23
D17-D31 D17-D31
CLK CLK
*DS *DS
R/*W R/*W
SIZ0 SIZ0
SIZ1 SIZ1
The following pins are wire-wrapped directly to the 68020's pins:
68851 to 68020
---------------------------
FC0-FC2 FC0-FC2
DSACKx DSACKx
*BERR *BERR
*HALT *HALT
*RESET *RESET
The following pins are wire-wrapped to the 68000's connector. The traces of
the 68000 connector leading to other chips are cut:
68851 to 68000 (traces cut)
----------------------------------------
PA8-PA23 A8-A23
The following pins are wire-wrapped to the 68020. The traces of these pins
leading to other chips are cut.
68851 to 68020 (traces cut)
----------------------------------------
*LAS *AS pin L1
*LBRO *BR pin B3
*LBGI *BG pin B2
*LBGACK *BGACK pin A1
The following pins are connected to where the above four 68020 pins were
leading:
68851 to Somewhere
-------------------------------
*PAS U10,3 U5,18
*PBR U1,13
*PBG U5,9
*PBGACK U1,12 U5,8
The following are connected on the 96-pin Din through a 4.7K resistor:
68851 to 96-pin Din (4.7K)
---------------------------------------
*ASYNC Vcc B1
*LBRI Vcc B2
*RMC Vcc B3
FC3 Gnd B32
The following are optionally connected directly to the 68020:
68851 to 68020
---------------------------
LA24 A24
LA25 A25
... ...
The following are not connected:
68851
-----
D0-D15
PA24-PA31 (a few of these may be connected to the 68020 if desired)
*LBGO
*CLI
DBIS
The A0-A7 pins of the PMMU have to be latched before they are send to the
68000 slot. These pins are also connected to the 96-pin Din. We use a
74F373 (Octal transparent D-type latches) chip.
68851 to 74F373 (U13)
----------------------------------
A0 1D pin 3
A1 2D pin 4
A2 3D pin 7
A3 4D pin 8
A4 5D pin 13
A5 6D pin 14
A6 7D pin 17
A7 8D pin 18
74F373 to Whatever
------------------------------
1D U7,3 (68020 A0 trace is cut)
2D 68000 A1 \
3D 68000 A2 \
4D 68000 A3 \
5D 68000 A4 (68000 traces leading elswhere are cut)
6D 68000 A5 /
7D 68000 A6 /
8D 68000 A7 /
A 74F00 (Quad AND gates) chip is used to control the 74F373. The logic
functions are G = *( *BGACK020 & *AS020 )
OC = *( *( *PAS & *(*PBG) ) & *PBGACK )
+---\
*BGACK 020 -----+ )
|NAND)*----- *C U14,11
*AS 020 -----+ )
+---/
4.7K +---\
Vcc ---/\/\/\/---+ ) +---\
|NAND)*-----+ ) +---\
*PAS 851 --------+ ) |NAND)*-----+ )
+---/ +--+ ) |NAND)*---- *OC U14,1
| +---/ +--+ )
*PBG 851 -----------------+ | +---/
|
*PBGACK 851 --------------------------+
In the 68851 User's Manual, they use a negated-input OR gate instead of the
third NAND gate. I do not have any practical experience designing electronic
circuits, but could that actually be a wired-or circuit. Would that look like
this?
4.7K +---\ 4.7K
Vcc ---/\/\/\/---+ ) +---\ +---/\/\/\/--- Vcc
|NAND)*-----+ ) |
*PAS 851 --------+ ) |NAND)*--+------ *OC U14,1
+---/ +--+ ) |
| +---/ |
*PBG 851 -----------------+ |
|
*PBGACK 851 --------------------------+
Capacitors on 74F74: .1 uF monolithic
Capacitors on 74F373: .1 uF monolithic
Capacitors on 68851: 2x .01 uF ceramic, 4x .1 uF monolithic, 4x .47 uF
1x 4.7 uF, 1x 15.0 uF
Once again, I beg you to take a good look at this. It is crucial to my
project, and if the project is successful, the results will have a resounding
impact on the Amiga community.
-------------------------------------------------------------------------
"An operating system without Name: Valentin Pepelea
virtual memory is an operating Phone: (613) 233-1821
system without virtue." Bitnet: 451061@uottawa
- ancient Inca proverbpapa@pollux.usc.edu (Marco Papa) (12/14/88)
In article <5933@louie.udel.EDU> 451061%UOTTAWA.BITNET@cornellc.cit.cornell.edu (Valentin Pepelea) writes: >I need to add a 68851 MMU into the Lucas board for a 4th year University >project I am working on. The design, as described by the block diagram of >page B-2 of the MC68851 User's Manual seems quite simple, but I don't have >enough practical electronics experience to be certain about it. Here is a >description of the schematic I came up with; Please move this discussion to comp.sys.amiga.tech. Thank you. -- Marco Papa 'Doc' -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= uucp:...!pollux!papa BIX:papa ARPAnet:pollux!papa@oberon.usc.edu "There's Alpha, Beta, Gamma and Diga!" -- Leo Schwab [quoting Rick Unland] -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=