dillon@HERMES.BERKELEY.EDU (Matt Dillon) (06/13/89)
:Well, yes and no. The caches on both '030 and '020 are straight mapped 256 ^ :byte caches. They're organized a bit differently, the '030 caches are both direct mapped. :-) :Note that this is all very '020/'030 specific; the '040, or either '020/'030 :with external cache, will no doubt behave very differently. You'll likely :have more obvious cache support in the OS by then, though... From the rumors I've heard, the 040 will have two 4K caches, one for data and one for code, each is 4-way associative so it won't work. The 68040 will have a harvard architecture internally. Motorola commented that it had learned a lot from the 88000 series and many 040 instructions will achieve single cycle execution. Intel's 80486 will have a single 8K 4-way associative cache (same total amount). I seem to remember them saying that the chip internal busses will be 128 wide but can't be sure. As far as I can tell, they are moving towards maximum functional integration and just throwing more bits at their busses to achieve the throughput... sort of like their silly little Risk chip that began as a coprocessor. -Matt
daveh@cbmvax.cbm.commodore.com (Dave Haynie) (06/13/89)
Sounds like you've got some good rumor sources. Of course the '030 has an internal harvard architecture, so you'd have a good reason to expect the '040 to have one as well. The '040 design does look alot like an 88x00 system; separate MMU/ATC/Cache units for both I and D, 4-set associative like the 88200. Also, they're physically mapped, as opposed to the logically mapped caches on the '030, which is required for bus snooping, and can result in fewer cache flushes in a system that knows how to use a physical cache. I guess the main point against physical caches to date has been the speed loss, but Motorola seemed to have that pretty well taken care of in the '030 anyway, so the '040 should be just fine. The Intel thing with it's single big cache seems an obvious compromise to the world of MS-DOS. Extra wide buses to try and wring more performance out of it is a good idea, but it all ultimately gets crammed into the internal 32 bit bus it looks. -Dave
mph@behemoth.phx.mcd.mot.com (Mark Huth) (06/15/89)
Current specs for '040 - released, not internal rumors - 68882 compatible FPU Internal Harvard Architecture On chip PMMU Two 4k caches- in physical address space, simultaneously accessible Two ATC - simultaneous address translation for data and instructions Bus snooping for cache coherency '030 object compatible Concurrent FPU, IPU, MMU/BIU execution. Look for it in 25,33,50 and possibly 100 MHz versions. Mark Huth