axjjb@acad3.fai.alaska.edu (BRYANT JOHN J) (11/08/89)
I am hopelessly confused about the 25 mhz accelerator board. What do they mean by 32 bit ram? Is it accessing Ram at 32 bit increments? I am also wondering what is the exact bit access of the cpu..(ie..16 or 32) I have owned my amiga for 3 months and am trying to learn as much as possible. Any help would be appreciated. Thanks. Joe. Email axjjb@acad3.fai.alaska.edu
kim@beowulf.ucsd.edu (Geoffrey K Kim) (11/08/89)
In article <649@milton.acs.washington.edu> axjjb@acad3.fai.alaska.edu writes: >I am hopelessly confused about the 25 mhz accelerator board. What do they mean >by 32 bit ram? Is it accessing Ram at 32 bit increments? I am also wondering >what is the exact bit access of the cpu..(ie..16 or 32) I kinda had a related query regarding the '020 and '030 CPU cards: Isn't the Amiga's bus still only 16 bits wide? Since all video data has to be sent over this, doesn't this present a bottleneck? (I'd really like an A2000 with the next '030 board from CBM, but this question has kinda been lurking in the background.) +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | kim @beowulf.UCSD.EDU (Home of the Garden Weasles) | | "... ENGAGE!" -- Jean Luc Picard, STTNG | +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
daveh@cbmvax.UUCP (Dave Haynie) (11/09/89)
in article <649@milton.acs.washington.edu>, axjjb@acad3.fai.alaska.edu (BRYANT JOHN J) says: > > I am hopelessly confused about the 25 mhz accelerator board. What do they mean > by 32 bit ram? Is it accessing Ram at 32 bit increments? I am also wondering > what is the exact bit access of the cpu..(ie..16 or 32) On the basic Amiga, all memory is accessed by the 68000 on a 16 bit wide data bus. This is of course a perfect match to the CPU, because the 68000 only has a 16 bit data bus. Most accelerator cards use either the 68020 or 68030, both of which have a 32 bit wide external data bus (the 68030's internal data bus is actually 64 bits wide; there are separate 32 bit paths for Instruction and Data). While both chips can dynamically size their logical bus for 8, 16, and 32 bit transfers, the 32 bit transfer is the most efficient. In fact, due to the way these chips pre-fetch instructions, they're actually less efficient on a 16 bit bus than a 68000 (if you turn off the caching, even fast 68020s or 68030s will run as slow or slower than the 68000 in most things on a 16 bit bus). So to really take advantage of a 68020 or 68030 (for anything other than its floating point unit), you need memory with a full 32 bit wide bus. > Joe. -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
raz%kilowatt@Sun.COM (Steve -Raz- Berry) (11/10/89)
In article <7395@sdcsvax.UCSD.Edu> kim@beowulf.UCSD.EDU (Geoffrey K Kim) writes: >I kinda had a related query regarding the '020 and '030 CPU cards: Isn't >the Amiga's bus still only 16 bits wide? Since all video data has to be >sent over this, doesn't this present a bottleneck? Huh? This is incorrect. Have you forgotten about the custom graphics chips? Denise would be very offended if she heard you say this. Video data is kept in CHIP ram. The custom chips are told where the start of the display is kept in memory and they do all the display fetching and display operations (not to mention the other tasks they perform). The CPU only has to diddle with some registers (mostly). You are right about 16bits being a bottle neck, just not for the reason you mentioned. Dave Haynie just posted an description on why this is so. >(I'd really like an >A2000 with the next '030 board from CBM, but this question has kinda been >lurking in the background.) I hate when that happens. ;-) >| kim @beowulf.UCSD.EDU (Home of the Garden Weasles) | --- Steve -Raz- Berry Last day for the archiver: 11/17 UUCP: sun!kilowatt!raz ARPA: raz%kilowatt.EBay@sun.com KILOWATT: sun!kilowatt!archive-server archive-server%kilowatt.EBay@sun.com