a186@mindlink.UUCP (Harvey Taylor) (01/11/90)
In <9242@cbmvax.commodore.com>, bob@cbmvax.commodore.com writes: | | [re A1000 & Fat Denise] | This information is strictly a hypothetical answer to a hypothetical | question. | | PS: I designed the new Denise, [...] | Ah someone in the know & open to hypothetical questions. ;-) Let's say I had a VLSI custom chip set implemented in NMOS [about 2.5 or 3 micron design], and I wished to convert it to CMOS [about 1.2 to 1.5 micron design], support a higher clock rate (maybe 28MHz) and change the bus width to 32 bits. Just as a hypothetical problem, mind you, what sort of timeframe would we be talking about? What might be the estimated cost of such a design process? Can this kind of thing be simply run through a silicon compiler? Does the CBM fab plant, (what's it called, MOS?), have the 1.5 micron CMOS capability? <-Harvey "So far all seemed fair and square. The customer got what he paid for -- twice the performance for not quite twice the price. However IBM never let on to the customer that to double the printer's speed required only that a single rubber belt be moved from one set of pulleys to another." -Big Blue:IBM's Use & Abuse of Power by Richard T. Delamarter Harvey Taylor Meta Media Productions uunet!van-bc!rsoft!mindlink!Harvey_Taylor a186@mindlink.UUCP
bob@cbmvax.commodore.com (Bob Raible - LSI Design) (01/16/90)
A very interesting hypothesis. Too bad company guidelines do not permit me to comment on future product plans. On the other hand I do listen to the network and have heard several worthwhile suggestions. Unfortunately there are several topic areas that the conversation must remain one-sided. On the other hand you might take comfort in the fact that I and others of my ilk (silicon slingers ???) are extremely busy and are indeed constructively employed. At this time I will return to my grotto and meditate on "twisty little lines of aluminum and polysilicon, all alike". PS: Did I defeat the line-eater yet?