peter@cbmvax.commodore.com (Peter Cherna) (02/01/90)
In article <201@modcomp.UUCP> srp@modcomp.UUCP (Steve Pietrowicz) writes: >In the Jan. 29, 1990 issue of EE Times, there's an ad from Motorola >listing companies that will be supporting the 68040. Commodore's in >that list. Interestingly enough, Apple isn't. >-- >SR Pietrowicz UUCP: ...!uunet!modcomp!srp CIS: 73047,2313 > 73047.2313@compuserve.com I presume you mean the two page spread entitled "Look Who's Pushing 40". The ad has about ten large logos of companies that are in, as well as about twenty that are listed just by name. Commodore has a nice big logo. Sun is not listed (no surprise). Atari is not listed. Apple is not listed(!). NeXT is not listed(!!). Don't ask me why not... Incidentally, I'm told that the 68040 shown in the ad is actual size (about 2" x 2"). Peter -- Peter Cherna, Software Engineer, Commodore-Amiga, Inc. {uunet|rutgers}!cbmvax!peter peter@cbmvax.cbm.commodore.com My opinions do not necessarily represent the opinions of my employer.
navas@cory.Berkeley.EDU (David C. Navas) (02/01/90)
In article <201@modcomp.UUCP> srp@modcomp.UUCP (Steve Pietrowicz) writes: >In the Jan. 29, 1990 issue of EE Times, there's an ad from Motorola >listing companies that will be supporting the 68040. Commodore's in >that list. Interestingly enough, Apple isn't. Of course, didn't you know that the RSN A3000 w/1.4 and new Denise includes the brand new 25MHz 68040? :) :) :) Seriously, does anyone know if there is any potential for use of the 68040 by Commodore? >SR Pietrowicz UUCP: ...!uunet!modcomp!srp CIS: 73047,2313 David Navas navas@cory.berkeley.edu
smaug@eng.umd.edu (Kurt Lidl) (02/01/90)
In article <201@modcomp.UUCP> srp@modcomp.UUCP (Steve Pietrowicz) writes: >In the Jan. 29, 1990 issue of EE Times, there's an ad from Motorola >listing companies that will be supporting the 68040. Commodore's in >that list. Interestingly enough, Apple isn't. Interestingly enough, the Motorola booth at the UniForum show had a sample of the '040 under a microscope, so we could all "ooohhh" and "aahhhh" at it :-) The '040 doc that they were giving away listed *both* Apple and Commodore as having development systems or something like that for the '040. The Commodore person (Keith Gabryelski) showing off SysVR4 unix on the '030 equipped Amiga refused to comment on any products that Commodore may or may not be developing. Sometimes those wacky Commodore guys are just *no* fun. :-) And yes, indeed, the unix ran, X11 ran, and the multiple screen support on the Moniterm monitor that they had running was really neato-keen. The last issue of Byte has a little article on the '040, but it makes it sound ho-hum, even though we all know the truth. Byte made the '486 sound like the best thing since sliced bread when it was introduced. Such is the life of a computer rag gone bad. -- /* Kurt J. Lidl (smaug@eng.umd.edu) | Unix is the answer, but only if you */ /* UUCP: uunet!eng.umd.edu!smaug | phrase the question very carefully. */
es1@cunixb.cc.columbia.edu (Ethan Solomita) (02/02/90)
In article <21635@pasteur.Berkeley.EDU> navas@cory.Berkeley.EDU.UUCP (David C. Navas) writes: > >Seriously, does anyone know if there is any potential for use of >the 68040 by Commodore? As Commodore is on the list of developers of the 68040, and Motorola put a big Commodore logo in the advertisement, I would assume the we will eventually see a 68040 Amiga, at least one will be worked on. I'd be very surprised if Commodore didn't have to pay money to be on developer status. -- Ethan CIS: 70137,3271 Columbia: es1@cunixb.cc.columbia.edu
swarren@convex.com (Steve Warren) (02/02/90)
In article <5623@udccvax1.acs.udel.EDU> don@vax1.acs.udel.EDU (Donald R Lloyd) writes: > I wonder if there will ever be a 68050... a large number of >Motorola's biggest customers seem to be switching over to RISC technology. >In what direction will future Amigas go?... Well, to a large degree the 68040 *is* a RISC chip, unless you want to be a purist ;^). If you told a designer, "get as close as you can to RISC, but make it execute the 680x0 instruction set," then you would probably be most pleased if he produced something like the 68040. It has a six-level pipeline and achieves 1 cycle/instr. for the majority of instructions. That is why it beats most of the current RISC chips in performance (20 MIPS @25 MHz, ~4 MFLOPS) (assuming they are VAX- equivalent MIPS) (I know - big assumption - but perhaps not presumptuous). I think that as long as there is a 680x0 processor available with performance in the same magnitude range as current RISC processors it will continue to be utilized. A new processor architecture must be *significantly* faster to make it worthwhile to loose your software base. For a significant number of packages it would not simply be a matter of recompiling. Binary compatability is a big win for the 68040. I'm ready for my '040 LUCAS ;^). The chip is $800/sample, but you get the MMU and FPU on chip. Such a deal! ;^) I have no doubt there will be an '050, either. > ... Is there any real-world advantage >to RISC over CISC, other than being able to run lightning-fast benchmarks >to impress customers? ... Well, yes, there is, to some extent. Because the RISC processor eliminates instructions that take up disproportionate chip real-estate or require multiple cycles to execute there are these advantages: 1) Chip area that would have been used to implement sub-optimal instructions can be used for pipelining and multiple function units and extra cache, so that the extra instructions are traded for performance increases in the remaining instructions. 2) There are no multi-cycle instructions, so pipelines are less likely to get backed up by register hazards and the like. Motorola apparently did two things to overcome these advantages. 1) They went to an extremely dense process (1.2 million transisters), so that they were able to include the same performance-boosting features that smaller RISC processors include, while also including the suboptimal instructions needed for 68000 code-compatability. 2) They spent a *lot* of time analyzing and characterizing typical 680x0 applications to find out where problems would show up in the pipelines, and then implemented features that would minimize these problems. This means that the pipelines stay full most of the time. I have seen postings from several different individuals in comp.arch that indicate that RISC code is ~1.2-1.4 times as large as equivalent CISC code (due to simpler instructions). So if (as was reported) the '040 requires an average of 1.3 cycles per instruction, and executes code that is about 1.3 times denser than comparable RISC processors, it sounds to me like they are just about breaking even. But you can't drop that RISC chip into an Amiga and run Dpaint, can you? ;^) >... Aren't the Amiga's custom chips semi-RISC-ish? [...] Hmmm...the custom chip-set doesn't form a general purpose computer.
evgabb@sdrc.UUCP (Rob Gabbard) (02/02/90)
In article <201@modcomp.UUCP>, srp@modcomp.UUCP (Steve Pietrowicz) writes: > listing companies that will be supporting the 68040. Commodore's in > that list. Interestingly enough, Apple isn't. The hot rumor buzzing around about Apple these days is that there next generation of Macintosh will be based on the Motorola 88000 RISC chip. However, I did see mention of an '040 MAC somewhere. -- =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= Rob Gabbard (uunet!sdrc!evgabb) _ /| Workstation Systems Programmer \'o.O' Structural Dynamics Research Corporation =(___)= U =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
srp@modcomp.UUCP (Steve Pietrowicz) (02/03/90)
in article <1990Feb1.071944.7706@eng.umd.edu>, smaug@eng.umd.edu (Kurt Lidl) says:
- And yes, indeed, the unix ran, X11 ran, and the multiple screen support
- on the Moniterm monitor that they had running was really neato-keen.
Can you elaborate on "multiple screen support"? Do you mean like on
a stock Amiga?
--
SR Pietrowicz UUCP: ...!uunet!modcomp!srp CIS: 73047,2313
73047.2313@compuserve.comsmaug@eng.umd.edu (Kurt Lidl) (02/05/90)
In article <204@modcomp.UUCP> srp@modcomp.UUCP (Steve Pietrowicz) writes: >in article <1990Feb1.071944.7706@eng.umd.edu>, smaug@eng.umd.edu (Kurt Lidl) says: >- And yes, indeed, the unix ran, X11 ran, and the multiple screen support >- on the Moniterm monitor that they had running was really neato-keen. >Can you elaborate on "multiple screen support"? Do you mean like on >a stock Amiga? Using a combination of the Alt key and the function keys along the top of the keyboard, multiple screens were permitted. EG: Alt F10 produced the 1008x800 (or whatever the Viking/Moniterm produces) screen running X11 on it. Another function key produced a 80x24 text display that had a /bin/sh running in it. One of the "neat" things about this was the (and I quote) "infinnite baud console driver" -- there is a program called "truss" (If I remember correctly) that spews out all the system calls that a program is making... The screen was just a blur as this was happening... Pretty neat application for the blitter... At any rate, the display I saw was only on the Viking moniterm monitor -- I didn't think to ask about stock Amigas with just a 1080 monitor or the equivilent. PS -- the computer had a Boing! mouse on it. -- /* Kurt J. Lidl (smaug@eng.umd.edu) | Unix is the answer, but only if you */ /* UUCP: uunet!eng.umd.edu!smaug | phrase the question very carefully. */
seanc@pro-party.cts.com (Sean Cunningham) (02/06/90)
In-Reply-To: message from evgabb@sdrc.UUCP An 88000 based MAC...hehe, they haven't been too successful in making their '030 based machines completely compatable with software for the SE, etc., or even between the various '030 machines...I wonder what kind of headaches this will cause... Sean --->seanc@pro-party.cts.com
daveh@cbmvax.commodore.com (Dave Haynie) (02/16/90)
In article <5068@convex.convex.com> swarren@convex.com (Steve Warren) writes: >> ... Is there any real-world advantage >>to RISC over CISC, other than being able to run lightning-fast benchmarks >>to impress customers? ... >Well, yes, there is, to some extent. Because the RISC processor eliminates >instructions that take up disproportionate chip real-estate or require >multiple cycles to execute there are these advantages: I think you basically have it here. It takes a Motorola, or possibly an Intel, to build something reasonably competative using a more complex architecture. Not everyone can bang out a chip with 1.2 million transistors. At least from Motorola's claims, today's Sparc at 25MHz isn't quite as fast as the 68040 at 25MHz. That wouldn't surprise me a bit. However, the first Sparc chips were done in reasonably accessible gate arrays, something anyone can buy from a gate array house. The original Acorn RISC chip reportedly took only 20,000 or so gates to implement; it's not as fast as an '040 or a Sparc, but not bad. I think RISC gets you two things: - You don't have to be a full custom, state of the art VLSI house to build a reasonable, state of the art (performance-wise) CPU. - You might get things moving faster into new technologies, and therefore go faster, sooner. The last one is probably, more than anything, why Motorola got interested in RISC. The 88k was done in CMOS with a silicon compiler, and is much smaller than the 68040. You'll certainly see the 88k done in ECL or some other real fast technology much sooner than anything 68040-ish. There's already a reasonably small ECL chipset implementing the MIPS architecture in ECL. The only one I've heard of attempting to build an ECL 680x0 family machine, Edgecore, has lots of gate arrays and essentially built a minicomputer that just happened to execute 680x0 code, rather than a more cost effective micro. -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough
avrum@quiche.cs.mcgill.ca (Avrum WARSHAWSKY) (02/16/90)
In article <9697@cbmvax.commodore.com> daveh@cbmvax.cbm.commodore.com (Dave Haynie) writes: >I think you basically have it here. It takes a Motorola, or possibly an >Intel, to build something reasonably competative using a more complex >architecture. Not everyone can bang out a chip with 1.2 million transistors. >At least from Motorola's claims, today's Sparc at 25MHz isn't quite as fast >as the 68040 at 25MHz. > (etc.) There is one other point about RISC vs. CISC. In any machine, the maximum clock speed will be determined by the longest instruction or part of an instruction executed in a single cycle. In a CISC there are more instructions to worry about, so while a 25MHz 68040 may be faster than a 25MHz SPARC, it will probably be easier to manufacture a 50MHz SPARC than a 50MHz CISC machine using the same IC technology. --- Avrum Warshawsky - McGill University, Montreal Canada avrum@pike.ee.mcgill.ca
daveh@cbmvax.commodore.com (Dave Haynie) (02/20/90)
In article <2211@calvin.cs.mcgill.ca> avrum@calvin.cs.mcgill.ca (Avrum WARSHAWSKY) writes: >In article <9697@cbmvax.commodore.com> daveh@cbmvax.cbm.commodore.com (Dave Haynie) writes: >>It takes a Motorola, or possibly an Intel, to build something reasonably competative >>using a more complex architecture. Not everyone can bang out a chip with 1.2 million >>transistors. >In a CISC there are more instructions to worry about, so while a 25MHz 68040 may be >faster than a 25MHz SPARC, it will probably be easier to manufacture a 50MHz SPARC than >a 50MHz CISC machine using the same IC technology. Well, that's actually 1/2 my point. Or may two different quarters. The bottom line is that we're not likely dealing with the same IC technology. Most folks who are still doing serious work in CISC, such as Motorola and Intel, are also the folks who are pushing the barriers of the technology. As in my point above, it's probably much more difficult for someone to build a chip like the 68040 that can compete (no real results are in yet, but it's a pretty safe bet they're close) with a Sparc at the same speed. However, to date, no one's throwing a process like Motorola's 0.8um CMOS at something like Sparc. The original Sparcs were gate arrays! Something you or I could have made for us over at LSI Logic, Motorola, or Toshiba, for the right price. By implication, that's also the limit on the CISC technology. A simpler design, like a Sparc or an 88k, can move into faster silicon (or whatever) sooner. I'm sure we'll all have a few more grey hairs by the time we see an ECL or (more likely) GaAs process supporting 1.2 million transistors; the durn things just get far too hot. Which is why CMOS is doing so well. Only a few companies make 50MHz and up CPUs in CMOS; they may get a bit farther in BiCMOS, but chips with that many gates will be hitting hard limits in speed for some time to come. There's are already a RISC or two out in ECL gate array form, and certainly more on the way. So the bottom line is probably that neither side may be likely to use the same technology. At least until it stabilizes for longer than it has in the past. Which I hope never happens, that would get boring real fast. >Avrum Warshawsky - McGill University, Montreal Canada > avrum@pike.ee.mcgill.ca -- Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Too much of everything is just enough