tm@polari.UUCP (Toshi Morita) (04/12/90)
I sent mail to this guy but it keeps bouncing - Date: Tue, 10 Apr 90 11:32:56 edt From: Frank Glandorf <uunet!sdrc!gcglan> To: tm@polari.UUCP Subject: Re: 6502 MIPS In-Reply-To: your article <1484@polari.UUCP> News-Path: uunet!pilchuck!amc-gw!thebes!polari!tm Status: ORr >> I haven't quite figured out how to make rn/postnews/etc do my bidding yet, >> so please excuse my bumbling... >> >> Someone on the net mentioned that the 6502 would do 1 MIPS at 1 Mhz. This is >> not true. The fastest instructions on the 6502 (such as NOP, CLC, SEC, etc) >a. >> LDA/STA zeropage takes 3 cycles, LDA/STA absolute is 4 cycles...all the way >u. >> >> If a program consisted entirely of NOP, NOP, NOP...the 6502 would crank out >> (at 1 Mhz) 1/2 MIPS but for average programs I'd guesstimate an average of 4 >> cycles per instruction, or about a 4-to-1 Mhz to MIPS ratio. >> >While an instruction may take 2 to 7 cycles to complete the 6502's >pipelined architecture allows it to *complete* an instruction >nearly every cycle. I say nearly because a branch invalidates the >pipeline. Hence a 1Mhz 6502 has roughly the performance of a 3-4 Mhz >8080. >> Toshi Morita >> >> tm@polari 1) The 6502 isn't pipelined. The 6502 was selling for $25 in 1975 when the 6800 was selling for $200. The 6800 isn't even pipelined. 2) The 8080 is slow compared to a 6502 because the 8080 takes a LOT of cycles per instruction - something like 5-12. The 6502's speed is not due to pipelining - it's due to better bus bandwidth utilization (does a read or write almost every clock cycle). When an 8080 sits on the bus a lot of bus bandwidth is unused, especially during indexed addressing instructions. This is purely speculation, but I think the 8080 only has an 8 bit ALU, and when it does indexing off of a 16 bit register (like the HL register pair) it has to run the address calculations in two 8 bit ALU cycles, thus leaving the bus lonely. The 6502 only incurs a one cycle penalty for indexing on most instructions (LDA absolute is 4 cycles, LDA absolute,Y is 5 cycles)... 3) The 6502 doesn't complete an instruction "nearly every cycle". I program the 6502 every day for 10 hours. I use an American Automations hardware debugger. The trace history lists every single address that the CPU address bus has accessed and whether it was a read or write fetch. I can watch the ethereal opcodes and operands flowing across the data bus, in rhythm to the pulsings of the address bus. I can watch the 6502 fetch the mysterious tomes: "A9" (LDA immediate) "00" (immediate constant) "8D" (STA absolute) "F7" "B7" (absolute address, low-byte first) "01" (byte fetched from absolute address $B7F7). It takes six CPU cycles to perform LDA #00 STA $B7F7. Trust me. 4) The 6502 only incurs a one cycle penalty for conditional branching taken. There is no significant "pipelining" penalty. The single-cycle penalty is due to an ALU-addition/result to PC operation because conditional branches are PC-relative (BVC, BVS, BEQ, BNE, BMI, BPL, BCC, BCS, and anything else). Conditional branch not taken: 2 cycles, due to the CPU fetching two bytes (BNE *+5 is D0 04). Conditional branch taken is 3 cycles: fetch D0, fetch 04, then an ALU operation with result saved to PC. The only unconditional branch is JMP and is absolute, and takes 4 cycles, I think; fetch 4C, fetch low byte of address, fetch high byte of address, shove bytes to PC. No "pipelining penalty" on any branch instructions. 5) I've been doing 6502 assembly for the past four years; some for Origin (on Ultima V), some independently, and currently for Taito Software, Inc. Have you done any 6502 assembly? I'd suggest you buy a good 6502 databook before you spread any more misinformation. Sybex has a reasonably good one ("Programming and Interfacing the 6502"). I don't remember the ISBN, sorry! :) Toshi Morita ..!uunet!microsoft!uw-beaver!sumax!polari!tm
kms@uncecs.edu (Ken Steele) (04/14/90)
In article <1546@polari.UUCP>, tm@polari.UUCP (Toshi Morita) writes: > > > 1) The 6502 isn't pipelined. The 6502 was selling for $25 in 1975 when the 6800 > was selling for $200. The 6800 isn't even pipelined. > I don't quite see how the price of a chip determines the correct answer. You might also look at chapter 5 (section 5.1) of the 1975 MOS Technology manual where it is explicitly noted that the 6502 does pipeline. > > I'd suggest you buy a good 6502 databook before you spread any more > misinformation. Sybex has a reasonably good one ("Programming and > Interfacing the 6502"). I don't remember the ISBN, sorry! :) You might be refering to Marvin DeJong's "Programming & Interfacing the 6502" (1980, Sams & Co., ISBN 0-672-21651-5) or to Rodnay Zaks "Programming the 6502" (1978, Sybex, ISBN 0-89588-046-6). I found the DeJong book to be more informative. Let us now return from the past into TODAY :-) > > > Toshi Morita > ..!uunet!microsoft!uw-beaver!sumax!polari!tm Ken -- Ken Steele Dept. of Psychology kms@ecsvax.bitnet Mars Hill College kms@ecsvax.uncecs.edu Mars Hill, NC 28754 {some big name site}!mcnc!ecsvax!kms