daveh@cbmvax.commodore.com (Dave Haynie) (09/14/90)
In article <2956@corpane.UUCP> sparks@corpane.UUCP (John Sparks) writes: >rehrauer@apollo.HP.COM (Steve Rehrauer) writes: >>Ah, I'd imagine it'd take a bit fewer than 200,000,000, for whatever RISC >>architecture he chooses. If not, he should choose a different one. :-) >Actually since the article mentioned that it had downloadable micro-code, >wouldn't that meand that it would be neither RISC nor CISC, but something >new maybe.... ooohh I don't know... PISC? Programable blah blah blah? >I'll believe it when I see it. Maybe in another 10 years or so. But not today. Don't be so sure. I just read about a very interesting new architecture, called MISC (Minimal Instruction Set Computer). It's basically a Very Long Instruction Word computer, but without the problems. The idea of VLIW is to support many different functional units in a chip, each with its own instruction, on every cycle. So you provide a long instruction word, which has fields that provide instructions for each of your functional units. These instructions get created by clever scheduling, much like a RISC compiler trys to keep a pipeline full by ordering instructions in clever ways. The problem in the past has been that VLIW computers are hard to build. This MISC approach solves that problem my making each functional unit extremely simple and each instruction processed by this unit very basic. So you end up with instructions that aren't all that different than microcode on some machine, but you get a mess of them executed all at once. This particular architecture also has a few interesting thoughts given to multiprocessing and scheduling of CISC-like instructions on multiple MISC processors working together. The main drawback is that the thing "eats memory with a vengence". >John Sparks |D.I.S.K. Public Access Unix System| Multi-User Games, Email -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy Get that coffee outta my face, put a Margarita in its place!
FelineGrace@cup.portal.com (Dana B Bourgeois) (09/15/90)
Dave, your description of a MISC machine sounds a lot like the Forth Engine. Forth where the primitives are Opcodes and the secondaries are subroutines. Dana Bourgeois @ cup.portal.com