dan@srs.UUCP (03/28/87)
[This is my second attempt at posting- postnews & I are still getting used
to one another]
NEC V-series processor summary
28 February 87, by Dan Kegel (who has nothing to do with NEC whatsoever)
Data from a quick look at the '87 NEC Microcomputer Products catalog,
and has not been checked for errors...
The V20/V25/V30/V40/V50 CMOS processors share an instruction set which is a
superset of the 80186's; non-Intel extensions include BCD string math support,
ordered string comparisons, and bit and bit field operations.
All but the V25 can emulate the 8080, and have multiplexed data/address busses.
The V20/V30 are externally identical to the 8088/8086, but execute many
instructions faster, notably multiply and divide.
These processors are cheap and easily available.
The V25 is similar to the V20, but has separate data and address busses,
and includes on-chip peripherals (which appear to be custom jobs rather
than standard parts brought on-chip):
8 register banks with optional hardware context switching on interrupts
clock & wait state generator
2 16-bit timers
1 fixed time base counter
3 vectored interrupt input pins
2 USART serial I/O channels
2 DMA channels
3 8-bit parallel ports (some shared with other pin functions)
8 variable threshold input pins
9 bit DRAM refresh
The V25 is poorly specified in the '87 databook, and is probably not real yet.
The V40 and V50 are similar to the V20 and V30, respectively, but execute
many instructions in 10-20% fewer cycles, and include on-chip peripherals
(more like standard parts than those in the V25):
clock & wait state generator
3 16-bit timers (subset of Intel 8254)
7 vectored interrupt input pins (compatible with Intel 8259)
2 UART serial I/O channels (asynch. subset of Intel 8251)
4 DMA channels (compatible with NEC uPD71071)
9 bit DRAM refresh
8080 emulation summary
The V25 lacks 8088 emulation, but the V20/V30/V40/V50 all include it.
A mode bit in the flags register determines whether the 8080 or
the native instruction set is in effect.
8080 programs can call native subroutines directly, and native programs
can call 8080 programs using a special version of the INT instruction.
Normal interrupt routines are entered in native mode.
----------------------------------------------------------------------
Instruction Set Summary
80186 instructions are marked with a hash mark #.
Non-Intel instructions are marked with an asterisk *.
Instructions are listed by Intel mnemonics; non-Intel instructions are
listed by the NEC mnemonic except for INS and EXT, which are listed
as INSBF and EXTBF to avoid conflict with the Intel string I/O mnemonics.
Opcodes are given for V20 and 80186 instructions in hex for simple opcodes,
and in binary for opcodes having bit fields to be filled in. See the
table at the end of the file for bit field definitions.
V20 execution times are listed in clock cycles; if the instruction has a byte
and a word version, the byte and word version time are separated by a slash.
Times include operand I/O time, but not instruction fetch time, because
instruction fetch and execution can overlap.
It takes 4 clocks (plus any wait states) to fetch or store one byte for
V20/40, and 4 clocks to fetch or store 2 bytes for the V30/50.
Unlike the 8088, the V20 doesn't appear to insert a T5 state during IN & OUT.
On the 8-bit V20 and 8088, instruction and operand fetching usually take
longer than instruction execution, so true execution time is close to the
lower bound of (4 clocks/byte)*(# of bytes fetched or stored).
Mnemonic bytes clocks opcode Comments
on V20
--- Data Tranfer ---
MOV reg, reg 2 2
mem, reg 2-4 9/13
reg, mem 2-4 11/15
mem, imm 3-6 11/15
reg, imm 2-3 4
acc, [imm16] 3 10/14
[imm16], acc 3 9/13
segreg, reg16 2 2
segreg, mem16 2-4 11/15 ??
reg16, segreg 2 2
mem16, segreg 2-4 10/14 ??
LDS/LES reg16, mem32 2-4 18/26 ??
SAHF 1 3
LAHF 1 2
LEA reg16, mem 2-4 4
XLAT 1 9
XCHG reg, reg 2 3
mem, reg 2-4 16/26
AX, reg16 1 3
--- Repeat Prefixes ---
* REPC 1 2 65h For signed string comparisons
* REPNC 1 2 64h
REPZ 1 2
REPNZ 1 2
--- String & I/O Instructions ---
MOVS 1 11+8n/+16n n = number of repetitions
CMPS 1 7+14n/+22n (word times not given in book)
SCAS 1 7+10n/+14n
LODS 1 7+9n/+13n
STOS 1 7+4n/+8n
# INS 1 9+8n/+16n 0110110W
# OUTS 1 9+8n/+16n 0110111W
IN acc, imm8 2 9/13
acc, dx 1 8/12
OUT acc, imm8 2 8/12
acc, dx 1 8/12
--- BCD Instructions ---
* ADJBA 1 3 37h if (al&f>9 || AC) al+=6,ah++...
* ADJ4A 1 3 27h two nibble version
* ADJBS 1 7 3fh if (al&f>9 || AC) al-=6,ah--...
* ADJ4S 1 7 2fh two nibble version
ADD4S, SUB4S, and CMP4S operate upon length CL BCD strings at [SI] and ES:[DI].
They set CY, Z, and V if CL is even, but Z and CY are wrong if CL is odd.
Don't know if they obey the Direction Flag.
* ADD4S dst, src 2 7+19n 0f 20h n= number of BCD digits / 2
* SUB4S dst, src 2 7+19n 0f 22h
* CMP4S dst, src 2 7+19n 0f 26h
ROL4 and ROR4 rotate the nibbles of the given byte thru the low nibble of AL.
* ROL4 reg8 3 25 0f 28 11000reg
mem8 3-5 28 0f 28 mod000mem
* ROR4 reg8 3 29 0f 2a 11000reg
mem8 3-5 33 0f 2a mod000mem
--- Conversion Instructions ---
CBW 1 2
CWD 1 4-5
AAM 2 15
AAD 2 7
--- Arithmetic Instructions ---
ADD/ADC/reg, reg 2 2
SUB/SBB mem, reg 2-4 16/24
reg, mem 2-4 11/15
reg, imm 3-4 4
mem, imm 3-6 18/26
acc, imm 2-3 4
INC/DEC reg8 2 2
reg16 1 2
mem 2-4 16/24
MUL reg 2 21-30 / 21-30 ??
mem 2-4 27-36 / 27-36 ??
IMUL reg 2 33-47
mem 2-4 39-57
# reg16,reg16,imm8 3 28-34
# reg16,mem16,imm8 3-5 34-44
# reg16,reg16,imm16 4 36-42
# reg16,mem16,imm16 4-6 46-52
DIV reg 2 19-35
mem 2-4 25-35
IDIV reg 2 29-43
mem 2-4 35-53
NEG reg 2 2
mem 2-4 16/24
--- Comparison Instructions ---
CMP reg, reg 2 2
mem, reg 2-4 11/15
reg, mem 2-4 11/15
reg, imm 3-4 4
mem, imm 3-6 13/17
acc, imm 2-3 4
--- Logical Instructions ---
NOT reg 2 2
mem 2-4 16/24
TEST reg, reg 2 2
mem, reg 2-4 10/14
reg, imm 3-4 4
mem, imm 3-6 11/15
acc, imm 2-3 4
AND/OR/ reg, reg 2 2
XOR mem, reg 2-4 16/24
reg, mem 2-4 11/15
reg, imm 3-4 4
mem, imm 3-6 18/26
acc, imm 2-3 4
--- Bit Operation Instructions ---
* TEST1 reg, CL 3 3/3 0f 0001000W 11000reg
mem, CL 3-5 12/16 0f 0001000W mod000mem
reg, imm3/4 4 4/4 0f 0001100W 11000reg
mem, imm3/4 4-6 13/17 0f 0001100W mod000mem
* CLR1 reg, CL 3 5/5 0f 0001001W 11000reg
mem, CL 3-5 14/22 0f 0001001W mod000mem
reg, imm3/4 4 6/6 0f 0001101W 11000reg
mem, imm3/4 4-6 15/27 0f 0001101W mod000mem
* SET1 reg, CL 3 4/4 0f 0001010W 11000reg
mem, CL 3-5 13/21 0f 0001010W mod000mem
reg, imm3/4 4 5/5 0f 0001110W 11000reg
mem, imm3/4 4-6 14/22 0f 0001110W mod000mem
* NOT1 reg, CL 3 4/4 0f 0001011W 11000reg
mem, CL 3-5 18/26 0f 0001011W mod000mem
reg, imm3/4 4 5/5 0f 0001111W 11000reg
mem, imm3/4 4-6 19/27 0f 0001111W mod000mem
--- Bit Field Operations ---
INSBF writes the op2 low bits of AX to the op2 bits of memory starting
at ES:DI, bit offset op1. DI and op1 are updated afterwards for the next
iteration. Inserted bit fields may overlap byte boundaries.
(These instructions treat the reg fields according to mod=11, W=0.)
* INSBF reg8, reg8 3 35-133 0f 31 11regReg
reg8, imm8 4 35-133 0f 31 11000Reg
EXTBF loads the op2 low bits of AX from the op2 bits of memory starting
at DS:SI, bit offset op1. SI and op1 are updated afterwards for the next
iteration. Extracted bit fields may overlap byte boundaries.
* EXTBF reg8, reg8 3 35-133 0f 33 11regReg
reg8, imm8 4 35-133 0f 33 11000Reg
--- Rotates and Shifts ---
ROL/ROR/RCL/RCR/SHL/SAL/SHR/SAR
reg by 1 2 2 1101000W modTTTreg
mem by 1 2-4 16/24 1101000W modTTTmem
reg by CL 2 7+n 1101001W modTTTreg
mem by CL 2-4 19/27+n 1101001W modTTTmem
# reg by imm8 3 7+n 1100000W modTTTreg
# mem by imm8 3-5 19/27+n 1100000W modTTTmem
TTT: 0=ROL, 1=ROR, 2=RCL, 3=RCR, 4=SHL/SAL, 5=SHR, 7=SAR
--- Stack Operations ---
PUSH mem16 2-4 26
reg16 1 12
segreg 1 12
# all 1 67 60h
# imm 2-3 11/12 011010W0 byte is sign-extended
Pushf stores flags as follows (hi bit to low bit):
8080MODE:1:1:1:OF:DF:IF:TF:SF:ZF:0:AF:0:PF:0:CF
PUSHF 1 12
POP mem16 2-4 25
reg16 1 12
segreg 1 12
# all 1 75 61h
POPF 1 12
# ENTER imm16,imm8 4 * C8h 12 if imm8==0; else 19+8*(imm8-1)
# LEAVE 1 10 C9h
--- Control Transfer Instructions ---
CALL imm16 3 20
reg16 2 18
mem16 2-4 31
imm32 5 29
mem32 2-4 47
RET 1 19
pop-value 3 24
RETF 1 29
pop-value 3 32
JMP imm16 3 13
imm8 2 12
reg16 2 11
mem16 2-4 24
imm32 5 15
mem32 2-4 35
Jcc imm8 2 14/4 branch taken / not taken
JCXZ imm8 2 13/5
LOOP imm8 2 13/5
LOOPZ imm8 2 13/5
LOOPNZ imm8 2 14/5
--- Interrupt Instructions ---
INT 3 1 50
imm8 2 50
INTO 1 52/3
IRET 1 39 (slow!)
# BOUND reg16, mem32 2-4 76/26 62 modRegMem
* BRKEM imm8 3 50 0f ff Same as INT, but sets 8080 mode.
--- Coprocessor Interface Instructions ---
ESC imm3,imm3,imm3 2 2 11011xxx 11yyyzzz
imm3,imm3,mem 2-4 15 11011xxx modyyyMem
* FPO2 imm1,imm3,imm3 2 2 0110011x 11yyyzzz
imm1,imm3,mem 2-4 15 0110011x modyyyMem
WAIT 1 2+5n
--- CPU Control Instructions ---
CLC/STC/CMC 1 2
CLD/STD 1 2
EI/DI 1 2
HALT/LOCK 1 2
NOP 1 3 xchg ax, ax
--- 8080 Instruction Set Enhancements ---
RETEM 2 39 ED FD
CALLN imm8 3 58 ED ED
-------------------------------------------------------------------------
Bit field names:
W 1 bit word/byte flag 1 = word op, 0 = byte op;
mod 2 bits addressing mode, see table below
mem/reg 3 bits; meaning depends on mod and W fields:
mod=00 mod=01 mod=10 mod=11, W=0/1
000 [BX+SI] [BX+SI+imm8] [BX+SI+imm16] AL/AX
001 [BX+DI] [BX+DI+imm8] [BX+DI+imm16] CL/CX
002 [BP+SI] [BP+SI+imm8] [BP+SI+imm16] DL/DX
003 [BP+DI] [BP+DI+imm8] [BP+DI+imm16] BL/BX
004 [SI] [SI+imm8] [SI+imm16] AH/SP
005 [DI] [DI+imm8] [DI+imm16] CH/BP
006 [imm16] [BP+imm8] [BP+imm16] DH/SI
007 [BX] [BX+imm8] [BX+imm16] BH/DIflowers@ucla-cs.UUCP (03/30/87)
Has any one tried putting a V20 or V40 into a Zenith 181?
In general, how much does it improve things to install a V20 or V40 in
your system?
Margot Flowers Flowers@CS.UCLA.EDU ...!{ucbvax|ihnp4}!ucla-cs!flowers