bright@Data-IO.COM (Walter Bright) (12/25/87)
I know that the 8088, 8086, 80286 and 80386 have instruction prefetch queues. But do any of them do pipelining? I.e., is mov AX,BX add CX,AX add SI,DI slower than: mov AX,BX add SI,DI ;this can proceed before the previous instruction is ;completed add CX,AX I have read Intel's 286 and 386 Programmer's manuals, and can find no mention of either prefetch queues or pipelining. What I'm looking for is information on the prefetch queues and pipelining such that I can write code to wring maximum performance out of the chips. Thanks in advance...