friedl@vsi.UUCP (Stephen J. Friedl) (02/26/88)
The following is from Jerry Pournelle's column in _Byte_,
March 1988 (page 183). It is reproduced without permission.
[begin article]
"FAIR WARNING
"Every now and again I see computers -- usually offshore-
constructed clones -- run at amazing speds, but when I look in-
side, the critical parts are ordinary chips. 'We select the good
ones,' one exhibitor told me at COMDEX. 'Try a lot until we find
parts that work.'
"That sounds right, but it isn't, at least not in the case
of Intel chips. I've been talking to a former Intel designer,
and he tells me that Intel has very elaborate test equipment.
"When Intel makes a batch of expensive parts -- say, 386 or
387 chips -- they're put into the automated test setup and run at
the highest possible speed. Most of them fail those tests; the
few that pass are then certified for that speed and sold at a
premium.
"The rest of the parts are tested at lower speeds. Those
that pass get certified; the others are tested at still lower
speeds and become the 'ordinary' stock. A few don't pass at even
the minimum speed and are discarded.
"The point is, every 'ordinary' chip Intel sells has *failed
a test* [Jerry's emphasis] at higher speeds. That's guaranteed.
The failure the part experienced may not be critical. Intel has
excellent test equipment and can find failures that may never
show up in ordinary use -- but could could you know what the
failure was? It might be in a little-used area, but even
little-used features might be critical [like the early 80386 mul-
tiply? :-) SJF]. So while it's fun to crank up the speed on your
system, it's guaranteed that if you run Intel parts much above
their certified speed, you'll get failures. Murphy's law will
take care of the rest."
[end of article]
Please, no flames (about Intel QC or Jerry Pournelle). This
was interesting and I thought it would be relevant for the many
netlanders looking at faster machines. The above advice undoubt-
edly applies for all parts in your machine: look under the hood
before you buy!
Steve
--
Life : Stephen J. Friedl @ V-Systems Inc/Santa Ana, CA *Hi Mom*
CSNet: friedl%vsi.uucp@kent.edu ARPA: friedl%vsi.uucp@uunet.uu.net
uucp : {kentvax, uunet, attmail, ihnp4!amdcad!uport}!vsi!friedltsl@netsys.UUCP (Tom Livingston) (02/27/88)
In article <49@vsi.UUCP> friedl@vsi.UUCP (Stephen J. Friedl) writes: > > The following is from Jerry Pournelle's column in _Byte_, >March 1988 (page 183). It is reproduced without permission. > >[article deleted] > >look under the hood >before you buy! > > Steve >uucp : {kentvax, uunet, attmail, ihnp4!amdcad!uport}!vsi!friedl First, I wish to point out that this column had been written (I believe) around Nov '87. Now, according to Jerry Pournelle (jerryp on BIX), he got this information straight from the horse's mouth... But, he apparently made a bad assumtion -- he based his information JUST on 80386's and 80387, which were all being tested at that time (and are all still being tested). BUT, according to other BIXen, this is not true for other, more 'mature' type of chips, when quality tends to go up. When they've met the quotas for a certain (higher) speed, they are either not tested for that higher speed, or tested but sold in a lower speed lot. Also, Intel testing procedures are much more strenuos than normal conditions, testing extreames -- high/low voltages, hot and cold, and others, but still, they have failed -- they'll probably fail with yours. Not as large a caveat emptor, but still a think piece. _____________ / --/ __ _______ (_/ (_) / / / <_ Livingston { decuac,ihnp4 }!netsys!tsl
pavlov@hscfvax.harvard.edu (G.Pavlov) (02/27/88)
In article <49@vsi.UUCP>, friedl@vsi.UUCP (Stephen J. Friedl) writes: > > The following is from Jerry Pournelle's column in _Byte_, > March 1988 (page 183). It is reproduced without permission. > [begin article] > "FAIR WARNING ...... > (warning about boosting clock speed re Intel chips) Most (all ?) of the "fast" 80286 chips are not made by Intel. The article may have more to do with Intel's "war" with AMD than anything else ......... greg pavlov, fstrf, amherst, ny
wtm@neoucom.UUCP (Bill Mayhew) (03/02/88)
In a CMOS chip, power dissipation is proportional to clock speed. This is due to the fact that the principal cuase of power dissipation is that the complementary transistors in a gate's output stage are both in their ON states for a brief instant as the gate switches HIGH-->LOW or LOW-->HIGH. Essentially the +5 is connected directly to ground through the transistors. Incearsing the clock rate increases the number of state transitions per second and thus the average power consumed goes up. The attendant rise in temperature may casue the chip to fail. A low speed chip may run just fine at an elevated clock rate, but will fail prematurely due to thermal stress. 808x CPU chips are NMOS, thus they should have a power consumption independent of clock rate. Many clones do use NEC V series 808x work-alike chips which are CMOS. Some of the cheapo turbo clone boards I've seen for sale at local computer flea markets attempt to get away with using cheap parts by gluing their own heat fins onto the chips. Chip capabilities aren't the only problem associated with increasing a system's clock rate. At higher clock speeds, race conditions (the time it takes a logical condition to propagate though a logic network) can cause erronious addresses, etc to appear on the the bus. Race conditions may not occur consistently, and thus are difficult to trace down as the cuase of system crashes. On a system that I depended on reliability, I would probably decide to use a turbo coprocessor card, where the entire logic on the card (and chips) have been designed to operate properly at high clock speeds. --Bill
scott@hpcvca.HP.COM (Scott Linn) (03/05/88)
In NMOS technology, power is *not* totally independent of clock rate. There are two sinks where power goes: DC and AC. The DC power is dissipated when an inverter/nand/etc gate is driving low; the pullup to Vdd is a simple resistor which dissipates power when the other side is pulled to ground. The AC power is equal to C(Vdd^2)f, where C is the capacitive load, Vdd is 5V, and f is the toggling frequency of the driven node. If you have 16 drivers on the output bus driving 100 pf at 4 Mhz, you get .16W. Of course, if the DC power is 5W it's no big deal, but it does make a difference. The time where Vdd is shorted to GND does not always happen; the amount of "crowbar" current depends on the design. We always try to eliminate this current, and thus have just the C(Vdd^2)f power dissipation. Scott Linn HP - Northwest IC Division