misha@nsc.nsc.com (Michael Umansky) (03/08/88)
I am not sure if this has been discussed before but ... Does anyone know the relationship between DRAM access time and CPU/BUS speed in following combinations, I think I want to know the wait states needed: CPU/BUS DRAM ACCESS TIME SPEED 150ns 120ns 100ns 80ns 5 Mhz ? ? ? ? 6 Mhz ? ? ? ? 8 Mhz ? ? ? ? 10 Mhz ? ? ? ? 12 Mhz ? ? ? ? 16 Mhz ? ? ? ? 20 Mhz ? ? ? ?
Ralf.Brown@B.GP.CS.CMU.EDU (03/08/88)
In article <5003@nsc.nsc.com>, misha@nsc.nsc.com (Michael Umansky) writes: }Does anyone know the relationship between DRAM access time and CPU/BUS speed }in following combinations, I think I want to know the wait states needed: The following is a rough rule-of-thumb (and doesn't take into account caching's effect on wait states for 386 machines): 1. divide 1000 by CPU speed in MHz to get clock cycle in ns. 2. multiply by clocks per memory access 4 clocks+ws for 8088 (though I've never seen an 8088 with ws) 2 clocks+ws for 286 to get memory cycle time 3. divide by two. This gives the access time of the slowest memory chips you should even THINK of using*. If the memory is on an expansion card, you should use faster memory (unless the bus speed is lower than the CPU speed). * dynamic RAMs have cycle times of twice the access time. The access time is the amount of time from geting the complete address to having the value ready, and doesn't include the time needed to send the two halves of the address. Example: 10MHz/1ws AT clone 1. clock cycle is 100ns 2. 2clocks+1ws means 300ns memory cycle 3. use no slower than 150ns chips. (my 9.8MHz/1ws AT clone runs just fine with 150ns chips on the motherboard) -- {harvard,ucbvax}!b.gp.cs.cmu.edu!ralf -=-=- TalkNet: (412)268-3053 (school) ARPA: RALF@B.GP.CS.CMU.EDU |"Tolerance means excusing the mistakes others make. FIDO: Ralf Brown at 129/31 | Tact means not noticing them." --Arthur Schnitzler BITnet: RALF%B.GP.CS.CMU.EDU@CMUCCVMA -=-=- DISCLAIMER? I claimed something?