angeloh@vice.UUCP (Angelo Hung) (11/16/84)
SYSTEM DESIGN FOR TESTABILITY Dec. 17-20, 1984 sponsored by Oregon Graduate Center 19600 NW Walker Rd., Beaverton, OR 97006 This short course features: INTRODUCTION TO DFT Prof. Jacob Abraham, U. of Illinois SCAN PATH DESIGN AND ITS APPLICATION TO VLSI AND MICROPROCESSORS Dr. E. Eichelberger, IBM BUILT IN SELF TESTING Dr. T. Williams, IBM MICROPROCESSOR DESIGN EXPERIENCES WITH BIST Mr. J. Kuban, Motorola TESTABILITY ANALYSIS Dr. B. Krishnamurthy, Tektronix TEST GENERATION AND FAULT SIMULATION Dr. F. Wang, Tektronix FAULT MODELING Dr. R. Chandramouli, Intel DESIGN FOR TESTABILITY - A TRAVELER'S OVERVIEW Prof. D. Lenhert, Kansas State Univ. For details, please contact Francis Wang Course Coordinator (503) 627-6082 or Richard B. Kieburtz Chairman, Dept. of Computer Science & Engineering (503) 645-1121