tpf@pyr.gatech.EDU (Tom Friedel) (08/04/88)
In the text "Programming the 80386" it says `to calculate eleapsed time for an instruction, multiply the instruction clock count by the processor clock speed'. A MOV instrunction from register to register is 2 clock ticks; from register to memory is 2 and from memory to register is 4. My question is how is the elapsed time affected if the memory operand is in (1) a high-speed hardware cache and (2) `slow' memory. Tom Friedel - email responses welcome
Sorceress@cup.portal.com (08/06/88)
The clocks counts shown in the manual assume 0 wait state memory. Slower memory will add 1 or 2 wait states where the CPU is doing nothing, just hanging around waiting for memory to respond. In short the slower memory will simply make the instruction take longer to execute. Jan St Martin
haugj@pigs.UUCP (Joe Bob Willie) (08/09/88)
In article <6177@pyr.gatech.EDU> tpf@pyr.gatech.EDU (Tom Friedel) writes: >In the text "Programming the 80386" it says `to calculate eleapsed time for >an instruction, multiply the instruction clock count by the processor clock >speed'. > >A MOV instrunction from register to register is 2 clock ticks; from register >to memory is 2 and from memory to register is 4. > >My question is how is the elapsed time affected if the memory operand is in >(1) a high-speed hardware cache and (2) `slow' memory. the cycle times listed are for 0 wait state memory. in the case of CPU's with caches (and the 386 with it's separate bus section), these times may also be reduced by cache misses or other action taking place in the bus unit. thus, to get the actual times you need to know how many wait states the memory being used will add, unless your CPU has an I-cache or large instruction pipeline (as the 386 and 680[23]0 have on chip) then add in the wait states for the data reference, once again, unless you have a D-cache or other fancy hardware. the book mentioned above is NOT the Intel manual and does not list the range of values. Motorola's 68020 manuals are a good example of the range of cycle times you can see between cached, not cached and just plain weird times. -- jfh@rpp386.uucp (The Beach Bum at The Big "D" Home for Wayward Hackers) "Never attribute to malice what is adequately explained by stupidity" -- Hanlon's Razor