stevel@eleazar.dartmouth.edu (Steve Ligett) (08/08/88)
In article <22faf142@ralf> Ralf.Brown@B.GP.CS.CMU.EDU writes: N.B. The whole original article deleted here, and most of the reply from Ralf.Brown. > Dynamic RAMs require a memory > cycle time of twice the access time (due to setup and recovery times). I've seen this asserted several times, and maybe it's a convienent approximation. But it's not exactly correct. The cycle times are not so simply related to the access times. There is no simple equation that applies to all memory chips, from any maker, in any density, in any technology. You have to read the memory data sheets to get the two numbers, and then you'll have to read the data sheets from your microprocessor maker, and account for the time taken by the "glue" logic on the board to come up with required memory speed. Sometimes the access time will be the limiting factor, and sometimes the cycle time will be. With that as disclaimer, here is a table of access and cycle times for generic (dynamic ram) chips -- access cycle time time 200 ns 330 ns 150 ns 260 ns 120 ns 220 ns 100 ns 190 ns 85 ns 165 ns Some of the old chips had longer cycle times for these access times, and I've seen data sheets for some Hitachi products that have faster cycle times for these access times. Also, remember that these are memory chip times, not memory system times. Steve Ligett steve.ligett@dartmouth.edu or (decvax harvard ihnp4 linus)!dartvax!steve.ligett
boyne@hplvly.HP.COM (Art Boyne) (08/10/88)
bobmon@iuvax.cs.indiana.edu (RAMontante) writes: > I understand what a wait state does, but I have one simple question: what > IS a wait state? Is it a CPU clock cycle? Is it some portion of a clock > cycle related to the memory-chip timing (what relationship?)? Does it > come from some mysterious secret delay line somewhere? What??? When the 80x86 and 680x0 CPU chips access memory, they set up address (and if a write, data), then issue a start-memory-cycle indication (/S0 & /S1 on the 80286, /AS on the 680x0). The processor then waits for a memory complete indication from the rest of the hardware (READY on the 80x86, DTACK on the 680x0). Most systems are designed with a fixed time between the start flag and the complete handshake. Typically, either a shift register whose input is the start flag or a counter enabled by the start flag is used, with a predetermined shift bit/count generating the complete handshake. Meanwhile the CPU is in "waiting" state or condition (ie, doing NOTHING). Now, with fast memory, the access can be completed in 1 clock cycle. With slower memory, more than one clock cycle's worth of time is needed, and a different shift bit/count is used. This results in an delay which is an integral number of clock cycles. So, a wait state is: 1) one state in the state transition diagram of the CPU where the CPU does nothing, and 2) one clock cycle's worth of delay dictated by the slow memory. This description explains why simply changing the clock frequency of a CPU chip to speed up a system is very dangerous. The system waits the same number of (now shorter) clock cycles for every access, so each access is now faster. But unless the RAM chips involved support the faster accesses, disaster is only a few nano-seconds away! Hope this helps. Art Boyne, !hplabs!hplvly!boyne