[comp.sys.ibm.pc] IBM PC Bus ?

bharat@hprnd.HP.COM (Bharat Singh) (10/15/88)

I have seen several diiferent specification for the 'Channel Ready'
signal on the IBM PC bus.  The maximum time that a slave is allowed
to de-assert this signal (make it low) to extend the memory or I/O
cycle ranges from 2.5 micro-seconds (one publication) to 11 microseconds
in another publication.  Does any one in PC LAND know the reasoning
behind this 2.5 micro second limit?  Further, is there an authentic
publication on PC bus spec which can be relied upon?  

Need to know the answer soon, so please reply.