bradc@cognos.uucp (Brad Cameron) (12/22/88)
I am experimenting with placing a large amount of EPROM memory (~1 MB) in the extended memory area of a PC AT for the purposes of making software non-volatile (there are reasons why we want to use ROM :-)). My question is what access time specification on the EPROM chips is required for this device to function in a standard ( 8 MHz) AT bus without any additional wait states? Are EPROMs and RAMs equivalent when it comes to dealing with access time specifications? I intend to use 27512 EPROMs with 200 ns access time due to their relative low cost. I have a funny feeling that an extra wait state will have to be inserted into the bus cycle for these chips to be reliable. What are some simple ways to do this? (I know that the I/O CH RDY line has to be activated until the device is ready, but I am not sure of the standard ways of doing this). I would appreciate any thoughts on these topics. :-> Thanks in advance. -- Brad Cameron uucp: decvax!utzoo!dciem!nrcaer!cognos!bradc Cognos Incorporated mail: P.O. Box 9707, 3755 Riverside Drive, (613) 738-1440 Ottawa Ontario, Canada. K1G 3Z4