james@bigtex.cactus.org (James Van Artsdalen) (02/16/89)
In <111@.rsp.is>, orn@rsp.is (Orn E. Hansen) wrote: > NMI stands for Non Maskable Interrupt, and as the name implies this > actually cannot be masked. Not true. In fact, NMI is often off on a PC due to BIOS or debugger bugs (Microsoft's symdeb is particularly notorious for leaving NMI masked off). To experiment, just use a ball point pen to ground a data line on the bus. The processor itself can also mask NMI. > The system uses NMI for Parity Check and that can be masked with > $A0. So, if Shadowed Interrupts occur on the NMI Line, you can not > mask them out. Writing 0x80 to port 0x70 will disable NMI. Writing 0x00 to 0x70 will enable them. Only the high order bit is used: the low order bits are used as an index into the CMOS. NMI is automatically masked by the CPU after an NMI is acknowledged. NMI is re-enabled after IRET. An NMI handler must not exit without executing IRET, even if the return address is rigged. NMI is edge triggered, not level trigger. To compensate for this design flaw, the CPU latches the NMI signal during execution of an NMI routine. Therefore no NMI is actually lost as long as an NMI routine takes care to poll each and every potential source of NMI on each and every interrupt. In addition, and NMI handler must be prepared to handle spurious interrupts due to the following scenario: An NMI comes in, immediately followed by a second NMI. The second NMI is latched by the processor. The NMI handler sees and handles both NMIs. Upon IRET, the processor takes the latched NMI, but since the NMI source was handled in the preceding interrupt, no source is needing service the second time around. Send mail if you have further questions: I don't read news often. -- James R. Van Artsdalen james@bigtex.cactus.org "Live Free or Die" DCC Corporation 9505 Arboretum Blvd Austin TX 78759 512-338-8789