[comp.sys.ibm.pc] EOI's and Interrupt Service Routines

lynn@ivory.SanDiego.NCR.COM (Lynn Hedegard) (04/14/89)

 
 I  have  been working on a program for IBM compatibles which
 requires  processing  hardware  interrupts  from  a  special
 hardware device  known  as  the MPU-401.  I want the program
 to function correctly on both an XT and  AT.    The  MPU  is
 used to  interface  a computer with a synthesizer.  When you
 play a note (e.g. middle C)  on  the  synth,  the  MPU  will
 generate an  interrupt  on  IRQ2.    The  Interrupt  Service
 Routine (ISR) should then  read  three  bytes  from  a  port
 (typically:   90  3C  64)  into a buffer and return from the
 interrupt.  My question invloves the EOI sequence  performed
 prior to  the  IRET:   How many EOI's should be performed on
 the XT and how many should be performed on the AT?
 
 Let me begin by saying that i  have  been  researching  this
 problem  for  a  while  now  and  have looked at quite a few
 books.  While there are many good books on the subject,  the
 best  one,  in  my  opinion, is the MSDOS ENCYCLOPEDIA (ME).
 In the ME there is  whole  section  on  hardware  interrupts
 starting on  pg  409.  On pg 415 it says that an EOI must be
 performed prior to the IRET command.  Then on pg  419  there
 is  a  special  note  regarding AT's that says, "Durring the
 interrupt  sequence  the  corresponding  bit  in   the   ISR
 register  for  both 8259's is set, so two EOI must be issued
 to complete the interrupt service - one for  the  slave  and
 one for the master."
 
 I currently  have  my  MPU installed on an AT clone.  I have
 written a simple interrupt driven program  which  picks  off
 incoming  data from the MPU (via int's) and places them in a
 large buffer.  In my ISR i perform  two(2)  EOI's  prior  to
 the IRET  -and-  everything  works  fine!    The data in the
 buffer is consistant with what i expect. I also have  an  XT
 clone,  but  it  does  not  have  an  MPU  installed (budget
 constraints) so i have  not  performed  any  tests  on  that
 style machine.
 
 My hypothesis  is  as  follows:  Any program for the MPU (or
 any hardware interrupt type device) must  be  aware  of  the
 machine  class  (i.e.  XT  or AT) which it is running on and
 perform either one EOI (XT) or two EOI's(AT) accordingly.
 
 Well everyone, is this true?
 
 Lynn......