mserra@uvicctr.UUCP (mserra) (02/08/86)
WORKSHOP ANNOUNCEMENT
TECHNICAL WORKSHOP: NEW DIRECTIONS FOR IC TESTING
VICTORIA, CANADA, 18-19 MARCH 1986
Tentative Programme
The University of Victoria, (Dept. of Computer Science), the
University of Manitoba, (Dept. of Computer Science), and the
University of Bath (Dept. of Electrical Engineering), are
sponsoring a workshop on testing on March 18-19. The purpose
of the workshop is to present state-of-the-art developments
in the area of testing and design for testability. The
environment will encourage open discussion among the parti-
cipants and emphasize the exchange of information. Faculty
members and graduate students who are interested in the area
are cordially invited to attend. A tentative programme is
given below. For more information,registration, hotel
reservations, etc. contact:
Either Jon Muzio (604) 721 7220
or M. Serra (604) 721 7224
Dept. of Comp. Science, University of Victoria
Victoria, B.C. Canada
UUCP: {ubc-vision,uw-beaver,nrl-css}!uvicctr!jmuzio
or
{ubc-vision,uw-beaver,nrl-css}!uvicctr!mserra
EAN: jmuzio@uvunix.UVic.CDN
or
mserra@uvunix.UVic.CDN
Registration (to be received by Feb. 25):
CDN $60.00 includes
1 copy of proceedings containing all workshop papers
4 coffee breaks 2 lunches 1 banquet
Location:
The Executive House Hotel in the centre of beautiful down-
town Victoria, about 3 minutes walk from the inner harbour
and the Parliament Building.
Room Rates (spouse and children free in same room):
CDN $60.00 Single or Double
CDN $70.00 Twin
TENTATIVE PROGRAMME will include:
Comparing Causes of IC Failures,
E. J. MCCLUSKEY, Stanford University, U.S.A.
A General Scheme to Optimize Error Masking in Built-In Self-Testing,
Y. ZORIAN and V. K. AGARWAL, McGill University, Canada
Aliasing Probabilities of Some Data Compression Techniques,
FAULT DETECTION RESEARCH GROUP, University of Victoria, Canada
Counting and Signatures are almost orthogonal,
J. P. ROBINSON, University of Iowa, U.S.A.
Effectiveness Measures for Data Compression Techniques under
Unequally Likely Error Model,
N. R. SAXENA, Hewlett Packard, U.S.A.
Interrelationships Between Fault Signatures Based Upon
Counting Methods,
S. L. HURST, Bath University, England
On the Exhaustive Testing of Stuck-Open Faults in CMOS
Combinational Circuits,
D. M. MILLER and J. A. BATE, University of Manitoba, Canada
Testable CMOS Cells,
J. A. BRZOZOWSKI, University of Waterloo, Canada
The Testing of Integrated Circuits Incorporating Analogue
Sections,
A. P. DOREY, P. J. SILVESTER and R. J. BALL, University of Lancaster,
Concurrent Checking Techniques - A DFT Alternative,
I. L. SAYERS, D. J. KINNIMENT and G. RUSSELL, University of
Newcastle upon Tyne, England
Testability by Sum of Syndromes,
M. SERRA and J. C. MUZIO, University of Victoria, Canada
Matrix Methods for the Detection and Elimination of Redundancy in
Combinatorial Networks,
A. R. FLEMING, Hull University, England