igp@camcon.co.uk (Ian Phillipps) (05/18/89)
allbery@ncoast.ORG (Brandon S. Allbery) writes: >As quoted from <3181@looking.UUCP> by brad@looking.UUCP (Brad Templeton): >Optimization under RISC consists primarily of (1) recognizing that some >loops will run faster when "unwound" into linear code and (2) optimizing the >use of registers. And, maybe more important, re-ordering instructions so that the processor doesn't stall if a register value is still in the pipeline, and that the delay cycle after jumps is used constructively. These don't apply to any CISC processors I know of [ok. maybe mainframes, but no-one's given me one to play with]. -- UUCP: igp@camcon.co.uk | Cambridge Consultants Ltd | Ian Phillipps or: igp@camcon.uucp | Science Park, Milton Road |----------------- Phone: +44 223 420024 | Cambridge CB4 4DW, England |