ken@mcnc.org (Kenneth A. Whitfield) (09/25/89)
How does one determine what speed RAM is needed to acquire zero wait state in a 386-20 or 386-25 ?
plim@hpsgpa.HP.COM (Peter Lim) (09/26/89)
> / hpsgpa:comp.sys.ibm.pc / ken@mcnc.org (Kenneth A. Whitfield) / 8:47 pm Sep 25, 1989 / > How does one determine what speed RAM is needed to acquire > zero wait-state in a 386-20 or 386-25 ? > > ---------- Well, quite simply. As far as I know, the 386 in AT machines, like 286, uses at least 2 cycles for memory access. That is what it means by zero-wait-state. So, a 386-20 zero-wait cycle time would be 2 x 50 ns = 100 ns and a 386-25 zero-wait cycle time would be 2 x 40 ns = 80 ns. However, that is not all. You have to include the processor, decoder, RAS, CAS etc overhead and that differ from motherboard to motherboard (not to mention memory expansion board, which is why RAM on motherboard almost always run faster). These easily take up 30 to 40 ns. So you need at least 60 ns & 40 ns RAM respectively which, I am sure you realize, doesn't exist at the moment. The bottom line is there ain't any true zero-wait-state 386 in this world (except may be 386-16). What most manufacturer bragged about as zero-wait-state are slightly worse than one-wait-state. Then you have 3 cycles to play with and will probably need about 100 ns & 80 ns RAM (if the motherboard is well designed). This argument applies to the so called interleaved memory architecture machine which will run with one-wait-state (as opposed to the manufacturer's claim of zero-wait-state) when you are accessing alternating bank in the same page. When your program branches off to a far away place, the CAS (or was it RAS ?? Gee, I am never quite sure :-)) need to be setup again and the system usually insert another wait-state which takes you to two-wait-state. That's why such system is slightly worse than one-wait-state. For the higher end systems (i.e. those with cache memory). They will be operating at near to zero-wait-state by similar reasoning as above. Then it depends on whether the particular system insert one or two wait-state when you miss the cache; you might need either 60 ns & 40 ns RAM or 100 ns & 80 ns RAM. I have not personally come face to face with cached 386 yet, but my guess is that a cache miss will insert two-wait-state for most machine since the cache hit rate should be pretty high and there is not much point to waste money on speeding up the rare misses by using very high speed RAM. I hope that answer your question. :-) I think the very bottomline is to experiment with real RAM. When you get any real data please let me know (e-mail or notes), and what system are you having. Regards, Peter Lim. HP Singapore IC Design Center.