hadji@dasys1.UUCP (Toby A David) (10/07/89)
Hello World
I would very much appreciate opinions/reports on 20 or 25 mhz 386
motherboards. Micronics in particular.
The box I'm putting together will be mostly used for SCO Xenix286 and
eventually Unix 386. I intend to add 4 meg of ram.
The following questions come up..
1. Advantages to the 25mhz with cache memory board?
2. 100ns ram, or do you prefer the 80ns ?
3. Any problems with the memory interleave?
4. Optimum bus speed & wait states for the above operating systems?
5. Any problems with any particular MFM or ESDI controllers/drives ?
to the 25mhz (cache memory)
Any Email/Post opinions would be welcome. Thanks in advance.
--
Toby A David
Big Electric Cat Public UNIX
..!cmcl2!{ccnysci,cucard,hombre}!dasys1!hadjicliffhanger@cup.portal.com (Cliff C Heyer) (10/08/89)
Toby A David asks... >1. Advantages to the 25mhz with cache memory board? The cache is more useful with DOS because it is more likely that your code will stay in the cache. With UNIX the cache may get flushed at each context switch. But I suppose if you have a 128KB cache it may not all get flushed, but this would take some internals hacking to know for sure. 25MHz has a clock time of 40ns. If the code your running fits all in the cache you'll cook. BUT if your accessing slow main memory with 100ns DRAM which has 200ns cycle time, obviously you'll have many wait states. In fact, if your applications are not going to make use of the cache, then you might as well buy a 16MHz 386 with a clock time of 62ns, because the 25MHz will be waiting for memory all the time and only be running as fast as a 16MHz machine. >2. 100ns ram, or do you prefer the 80ns ? For 25MHz, clock time is 40ns. For 0 wait states you would have to be able to do a memory access in 40ns. The fastest DRAM is 60ns, BUT if you get 4MB 4-way interleaved 160ns DRAM then your cycle time would be 40ns ASSUMING you are reading bytes sequentially from memory. If your application does lots of random memory reads, though, you'll have wait states again. (PS interleaved memory is not new - computers like the DECsystem-10 and 20s of the 70s used it for the same reason.) If you want 0 wait states all the time, you'll need 40ns main memory which would have to be SRAM (static-RAM). But no board makers are making 40ns boards for 386 PCs - they are too busy making them to sell $50,000 workstations. I think if they made them for PCs the economy of scale would drive the price down, but then who would pay $50,000 for a workstation? >3. Any problems with the memory interleave? See #2. >4. Optimum bus speed & wait states for the above operating systems? You might as well stick with the 8MHz AT bus so you'll be sure all the boards you use will work. However, what you might want is a board that has a SCSI or ESDI controller "on board" BYPASSING the AT-bus with a direct channel to memory. On the other hand, I've been told that a "good" DMA board design will allow you to pump 1MB/sec through the AT bus, but most boards are slow because they are cheaper to make and customers arn't aware enough about speed to complain. >5. Any problems with any particular MFM or ESDI controllers/drives ? YES! You will find machines advertized as having 1.2MB/sec ESDI, but when you get the machine in your office and benchmark it you find it does only 300KB/sec raw I/O. I have yet to find out what is wrong with these mahcines. All I can say is don't buy before you see someone with an ACTUAL MACHINE that gives you raw I/O of 900KB/sec before you buy!
rac@sherpa.UUCP (Roger Cornelius) (10/09/89)
From article <22861@cup.portal.com>, by cliffhanger@cup.portal.com (Cliff C Heyer): - - For 25MHz, clock time is 40ns. For 0 wait states you - would have to be able to do a memory access in 40ns. The - fastest DRAM is 60ns, BUT if you get 4MB 4-way - interleaved 160ns DRAM then your cycle time would be - 40ns ASSUMING you are reading bytes sequentially from - memory. If your application does lots of random memory - reads, though, you'll have wait states again. (PS - interleaved memory is not new - computers like the - DECsystem-10 and 20s of the 70s used it for the same - reason.) If you want 0 wait states all the time, you'll Can you explain interleaved memory and what it's advantages are? What are the disadvantages of using Unix/Xenix on a non-interleaved system. The latest PC Mag. benchmarks several 33 mhz machines, and some of the systems had interleaved memory while others did not. Roger -- Roger A. Cornelius rac@sherpa uunet!sherpa!rac From vn Mon Oct 9 00:03:28 1989 Subject: Re: Micronics 386 motherboards Newsgroups: comp.sys.ibm.pc,comp.unix.i386 References: <22861@cup.portal.com> From article <22861@cup.portal.com>, by cliffhanger@cup.portal.com (Cliff C Heyer): - ->2. 100ns ram, or do you prefer the 80ns ? - For 25MHz, clock time is 40ns. For 0 wait states you - would have to be able to do a memory access in 40ns. The - fastest DRAM is 60ns, BUT if you get 4MB 4-way - interleaved 160ns DRAM then your cycle time would be - 40ns ASSUMING you are reading bytes sequentially from - memory. If your application does lots of random memory - reads, though, you'll have wait states again. (PS - interleaved memory is not new - computers like the - DECsystem-10 and 20s of the 70s used it for the same - reason.) If you want 0 wait states all the time, you'll Can you explain interleaved memory and what it's advantages are? What are the disadvantages of using Unix/Xenix on a non-interleaved system. The latest PC Mag. benchmarks several 33 mhz machines, and some of the systems had interleaved memory while others did not. Roger -- Roger A. Cornelius rac@sherpa uunet!sherpa!rac
jiii@visdc.UUCP (John E Van Deusen III) (10/10/89)
In article <22861@cup.portal.com> cliffhanger@cup.portal.com (Cliff C Heyer) writes: > > ... what you might want is a board that has a SCSI or ESDI > controller "on board" BYPASSING the AT-bus with a direct > channel to memory. That is what I DO want; an on board SCSI controller and an on board ethernet controller with at least TWO 32-bit private memory slots. Who sells these mother boards and what do they cost? As long as we have our soldering irons out, there isn't any need for any AT-compatible slots, since these peripherals can be accessed by a PC- based X terminal. We also might as well replace the 386 cpu with a high-mips risc processor, such as the M88000. What we have left is essentially a DG Maverick motherboard. Unfortunately, the latter is fatally flawed, because the Maverick board ALSO contains very expensive graphics coprocessors. I guess the hope springs eternal that the businesses of the world can be convinced to pay to put 22 MIPS on every desk top. The workstation paradigm has been so successful in the past that DG, DEC, and others are willing to blind themselves to the economies afforded by X terminals and follow SUN into the abyss. -- John E Van Deusen III, PO Box 9283, Boise, ID 83707, (208) 343-1865 uunet!visdc!jiii
davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr) (10/10/89)
In article <157@sherpa.UUCP>, rac@sherpa.UUCP (Roger Cornelius) writes: | Can you explain interleaved memory and what it's advantages are? Dynamic RAM has an access time and a cycle time. If you read one byte from the RAM it will take the access time, say 60ns. However if you go right back to that chip you can't get data in less than the cycle time, say 80ns. By putting the odd bytes in one bank and the even in another you avoid going to the same chip for two bytes in consecutive locations. High performance memory may be interleaved more than two ways to maximize the chance of hitting another chip when accesses are done, random or sequential. When Tandy released their first 386 machine some magazines got 20% more performance on the CPU than others. It seems that with only 1MB the interleave was disabled, giving 1 w/s on each access. There were claims that Tnady had sent out "souped up" machines for benchmarking, but these were proved false when adding memory to the "slow" machines made them fast. Many machines today require adding memory two banks at a time and don't offer disabling of interleave. Caching is another way of reducing the effective number of wait states, as is column static memory. Let some EE write the definitive posting. Oh yes, this is true for UNIX and DOS both. -- bill davidsen (davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen) "The world is filled with fools. They blindly follow their so-called 'reason' in the face of the church and common sense. Any fool can see that the world is flat!" - anon
jiii@visdc.UUCP (John E Van Deusen III) (10/11/89)
In article <969@crdos1.crd.ge.COM> davidsen@crdos1.UUCP (bill davidsen) writes: > ... > By putting the odd bytes in one bank and the even in another you avoid > going to the same chip for two bytes in consecutive locations. With a 386 we are accessing a 4-byte word with each memory access, so it is desirable to interleave words instead of bytes. Using 1 MB chips, eight megabytes are required for there to be two memory banks. -- John E Van Deusen III, PO Box 9283, Boise, ID 83707, (208) 343-1865 uunet!visdc!jiii